maikuanceliang.vhd

等精度测频 FPGA程序

--此模块的功能是测量脉宽
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY maikuanceliang IS
	PORT(
		 TCLK,CL,CLR:IN STD_LOGIC;
             ENDD,PUL:OUT STD_LOGIC
					);
END;
ARCHITECTURE behav OF maikuanceliang IS
 SIGNAL QQ:STD_LOGIC_VECTOR(3 DOWNTO 1);
 SIGNAL A0,B0,C0,F2:STD_LOGIC;
 SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
 S(0)<=QQ(3);S(1)<=QQ(2);
 PROCESS(CL,S)
 BEGIN
	IF CL='1'THEN F2<=TCLK;                 --如果起始信号为'1'则测高电平脉宽
    ELSE F2<=NOT TCLK;                         --否则测低电平脉宽
    END IF;
    IF S=2 THEN PUL<='1';                     --计高电平时间内标准信号的脉冲个数
    ELSE PUL<='0';
    END IF;
    IF S=3 THEN ENDD<='1';                    --计数结束的标志信号
    ELSE ENDD<='0';
    END IF;
 END PROCESS;
 A0<=F2 AND QQ(1);B0<=NOT A0;C0<=NOT F2;
 PROCESS(C0,CLR)
 BEGIN
	IF CLR='1'THEN QQ(1)<='0';                  
    ELSIF C0'EVENT AND C0='1'THEN QQ(1)<='1';
    END IF;
 END PROCESS;
 PROCESS(A0,CLR)
 BEGIN
	IF CLR='1'THEN QQ(2)<='0';
	ELSIF A0'EVENT AND A0='1'THEN QQ(2)<='1';
    END IF;
 END PROCESS;
 PROCESS(B0,CLR)
 BEGIN
	IF CLR='1'THEN QQ(3)<='0';
	ELSIF B0'EVENT AND B0='1'THEN QQ(3)<='1';
    END IF;
 END PROCESS;
END;