⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 wanzhenban.rpt

📁 等精度测频 FPGA程序
💻 RPT
📖 第 1 页 / 共 5 页
字号:
   -      2     -    A    05        OR2        !       1    3    0   32  |21mux:6|Y (|21mux:6|:5)


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                       d:\1hz-10mhz\wanzhenban.rpt
wanzhenban

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      40/ 96( 41%)    27/ 48( 56%)    22/ 48( 45%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       4/ 96(  4%)     0/ 48(  0%)    16/ 48( 33%)    1/16(  6%)      0/16(  0%)     0/16(  0%)
C:       3/ 96(  3%)     0/ 48(  0%)     0/ 48(  0%)    3/16( 18%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
15:      4/24( 16%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      4/24( 16%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
19:      4/24( 16%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
22:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                       d:\1hz-10mhz\wanzhenban.rpt
wanzhenban

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       35         TCLK
DFF         33         |COUNTER:20|BCLK
LCELL        2         |MAIKUANCELIANG:5|:293
INPUT        1         CLKB
LCELL        1         |MAIKUANCELIANG:5|:62


Device-Specific Information:                       d:\1hz-10mhz\wanzhenban.rpt
wanzhenban

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT       68         CLR


Device-Specific Information:                       d:\1hz-10mhz\wanzhenban.rpt
wanzhenban

** EQUATIONS **

CL       : INPUT;
CLKB     : INPUT;
CLR      : INPUT;
SEL0     : INPUT;
SEL1     : INPUT;
SEL2     : INPUT;
SPUL     : INPUT;
TCLK     : INPUT;

-- Node name is 'DATA0' 
-- Equation name is 'DATA0', type is output 
DATA0    =  _LC2_B21;

-- Node name is 'DATA1' 
-- Equation name is 'DATA1', type is output 
DATA1    =  _LC4_A19;

-- Node name is 'DATA2' 
-- Equation name is 'DATA2', type is output 
DATA2    =  _LC6_A19;

-- Node name is 'DATA3' 
-- Equation name is 'DATA3', type is output 
DATA3    =  _LC2_B17;

-- Node name is 'DATA4' 
-- Equation name is 'DATA4', type is output 
DATA4    =  _LC1_B17;

-- Node name is 'DATA5' 
-- Equation name is 'DATA5', type is output 
DATA5    =  _LC7_B15;

-- Node name is 'DATA6' 
-- Equation name is 'DATA6', type is output 
DATA6    =  _LC5_B16;

-- Node name is 'DATA7' 
-- Equation name is 'DATA7', type is output 
DATA7    =  _LC2_B14;

-- Node name is 'EEND' 
-- Equation name is 'EEND', type is output 
EEND     =  _LC1_A5;

-- Node name is 'START' 
-- Equation name is 'START', type is output 
START    =  _LC2_A9;

-- Node name is '|COUNTER:20|:50' = '|COUNTER:20|BCLK' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = DFFE(!_LC2_A19, GLOBAL( CLKB),  VCC,  VCC,  VCC);

-- Node name is '|COUNTER:20|:49' = '|COUNTER:20|BZQ0' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = DFFE( _EQ001,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ001 = !_LC2_A5 &  _LC5_A19
         #  _LC2_A5 & !_LC5_A19;

-- Node name is '|COUNTER:20|:48' = '|COUNTER:20|BZQ1' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = DFFE( _EQ002,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ002 = !_LC5_A19 &  _LC7_A19
         #  _LC2_A5 &  _LC5_A19 & !_LC7_A19
         # !_LC2_A5 &  _LC7_A19;

-- Node name is '|COUNTER:20|:47' = '|COUNTER:20|BZQ2' 
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = DFFE( _EQ003,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ003 =  _LC5_B15 & !_LC7_A19
         # !_LC5_A19 &  _LC5_B15
         #  _LC2_A5 &  _LC5_A19 & !_LC5_B15 &  _LC7_A19
         # !_LC2_A5 &  _LC5_B15;

-- Node name is '|COUNTER:20|:46' = '|COUNTER:20|BZQ3' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = DFFE( _EQ004,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ004 =  _LC1_B15 & !_LC4_B15
         # !_LC1_B15 &  _LC2_A5 &  _LC4_B15
         #  _LC1_B15 & !_LC2_A5;

-- Node name is '|COUNTER:20|:45' = '|COUNTER:20|BZQ4' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = DFFE( _EQ005,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ005 =  _LC2_B15 & !_LC3_B15
         #  _LC2_A5 & !_LC2_B15 &  _LC3_B15
         # !_LC2_A5 &  _LC2_B15;

-- Node name is '|COUNTER:20|:44' = '|COUNTER:20|BZQ5' 
-- Equation name is '_LC6_B15', type is buried 
_LC6_B15 = DFFE( _EQ006,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ006 = !_LC2_B15 &  _LC6_B15
         # !_LC3_B15 &  _LC6_B15
         #  _LC2_A5 &  _LC2_B15 &  _LC3_B15 & !_LC6_B15
         # !_LC2_A5 &  _LC6_B15;

-- Node name is '|COUNTER:20|:43' = '|COUNTER:20|BZQ6' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = DFFE( _EQ007,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ007 = !_LC8_B15 &  _LC8_B16
         #  _LC2_A5 &  _LC8_B15 & !_LC8_B16
         # !_LC2_A5 &  _LC8_B16;

-- Node name is '|COUNTER:20|:42' = '|COUNTER:20|BZQ7' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = DFFE( _EQ008,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ008 =  _LC3_B16 & !_LC8_B16
         #  _LC3_B16 & !_LC8_B15
         #  _LC2_A5 & !_LC3_B16 &  _LC8_B15 &  _LC8_B16
         # !_LC2_A5 &  _LC3_B16;

-- Node name is '|COUNTER:20|:41' = '|COUNTER:20|BZQ8' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = DFFE( _EQ009,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ009 =  _LC2_B16 & !_LC3_B16
         #  _LC2_B16 & !_LC7_B16
         #  _LC2_A5 & !_LC2_B16 &  _LC3_B16 &  _LC7_B16
         # !_LC2_A5 &  _LC2_B16;

-- Node name is '|COUNTER:20|:40' = '|COUNTER:20|BZQ9' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = DFFE( _EQ010,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ010 =  _LC4_B16 & !_LC6_B16
         #  _LC2_A5 & !_LC4_B16 &  _LC6_B16
         # !_LC2_A5 &  _LC4_B16;

-- Node name is '|COUNTER:20|:39' = '|COUNTER:20|BZQ10' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = DFFE( _EQ011,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ011 = !_LC1_B16 &  _LC5_A23
         #  _LC1_B16 &  _LC2_A5 & !_LC5_A23
         # !_LC2_A5 &  _LC5_A23;

-- Node name is '|COUNTER:20|:38' = '|COUNTER:20|BZQ11' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = DFFE( _EQ012,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ012 = !_LC5_A23 &  _LC6_A23
         # !_LC1_B16 &  _LC6_A23
         #  _LC1_B16 &  _LC2_A5 &  _LC5_A23 & !_LC6_A23
         # !_LC2_A5 &  _LC6_A23;

-- Node name is '|COUNTER:20|:37' = '|COUNTER:20|BZQ12' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = DFFE( _EQ013,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ013 = !_LC7_A23 &  _LC8_A23
         #  _LC2_A5 &  _LC7_A23 & !_LC8_A23
         # !_LC2_A5 &  _LC8_A23;

-- Node name is '|COUNTER:20|:36' = '|COUNTER:20|BZQ13' 
-- Equation name is '_LC1_A22', type is buried 
_LC1_A22 = DFFE( _EQ014,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ014 =  _LC1_A22 & !_LC1_A23
         # !_LC1_A22 &  _LC1_A23 &  _LC2_A5
         #  _LC1_A22 & !_LC2_A5;

-- Node name is '|COUNTER:20|:35' = '|COUNTER:20|BZQ14' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = DFFE( _EQ015,  _LC2_A19, !CLR,  VCC,  VCC);
  _EQ015 = !_LC1_A22 &  _LC2_A22
         # !_LC1_A23 &  _LC2_A22
         #  _LC1_A22 &  _LC1_A23 &  _LC2_A5 & !_LC2_A22
         # !_LC2_A5 &  _LC2_A22;

-- Node name is '|COUNTER:20|:34' = '|COUNTER:20|BZQ15' 
-- Equation name is '_LC7_A22', type is buried 

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -