fredevider.vhd

本频率计具有测周、测频、测量占空比等基本功能

library ieee;
use ieee.std_logic_1164.all;

entity Fredevider is
port
(clock:in std_logic;
  clk10Hz:out std_logic;
 clk100Hz:out std_logic;
 clk1KHz:out std_logic;
 clk10KHz:out std_logic;
 clk100KHz:out std_logic
 );
end;

architecture Devider of Fredevider is

constant N1:Integer:=4;
constant N2:Integer:=4;
constant N3:Integer:=4;
constant N4:Integer:=4;
constant N5:Integer:=4;

signal Counter1:Integer range 0 to N1;
signal Counter2:Integer range 0 to N2;
signal Counter3:Integer range 0 to N3;
signal Counter4:Integer range 0 to N4;
signal Counter5:Integer range 0 to N5;
--signal Counter5:Integer range 0 to 14;
signal Temp1,Temp2,Temp3,Temp4,Temp5:std_logic;
begin
  process(Temp2)
  begin
  if rising_edge(Temp2) then
    if Counter1=N1 then
       Counter1<=0;
       Temp1<=not Temp1;
    else Counter1<=Counter1+1;
  end if;
  end if;
  end process;

  process(Temp3)
  begin
  if rising_edge(Temp3) then
    if Counter2=N2 then
        Temp2<=not Temp2;
        Counter2<=0;
    else Counter2<=Counter2+1;
   end if;
  end if;
  end process;

  process(Temp4)
  begin
  if rising_edge(Temp4) then
      if Counter3=N3 then
       Temp3<=not Temp3;
        Counter3<=0;
      else  Counter3<=Counter3+1;
  end if;
  end if;
  end process;
  
  process(Temp5)
  begin
  if rising_edge(Temp5) then
    if Counter4=N4 then
       Counter4<=0;
       Temp4<=not Temp4;
    else Counter4<=Counter4+1;
  end if;
  end if;
  end process;
  
  process(clock)
  begin
  if rising_edge(clock) then
   if Counter5=N5 then
       Counter5<=0;
       Temp5<=not Temp5;
    else Counter5<=Counter5+1;

  --if Counter5=14 then
  -- Counter5<=0;
  -- m1<=not m1;
 -- else Counter5<=Counter5+1;
  --end if;
-- end if;
 
 --if falling_edge(clock) then
 --  if Counter5=8 then
   -- m2<=not m2;
   end if;
 end if;
 --Temp5<=m1 xor m2;
 end process;

   clk10Hz<=Temp1;
   clk100Hz<=Temp2;
   clk1KHz<=Temp3;
   clk10KHz<=Temp4;
   clk100KHz<=Temp5;
   
 end;