📄 plj.rpt
字号:
- 8 - A 09 OR2 0 4 0 1 |ZHANKONG:56|:1607
- 5 - A 09 OR2 0 4 0 1 |ZHANKONG:56|:1613
- 6 - A 07 OR2 0 4 0 1 |ZHANKONG:56|:1619
- 1 - A 07 AND2 s 0 2 0 1 |ZHANKONG:56|~1830~1
- 2 - A 07 OR2 s 0 3 0 1 |ZHANKONG:56|~1830~2
- 8 - A 08 AND2 s 0 2 0 17 |ZHANKONG:56|~1843~1
- 5 - A 01 OR2 s 0 4 0 1 |ZHANKONG:56|~1854~1
- 4 - A 24 AND2 s ! 0 3 0 2 |ZHANKONG:56|~1860~1
- 7 - A 24 OR2 s 0 4 0 1 |ZHANKONG:56|~1860~2
- 8 - A 24 OR2 s 0 3 0 1 |ZHANKONG:56|~1860~3
- 8 - A 13 OR2 s 0 4 0 1 |ZHANKONG:56|~1866~1
- 4 - A 13 OR2 s 0 4 0 1 |ZHANKONG:56|~1872~1
- 2 - A 01 AND2 s ! 0 3 0 5 |ZHANKONG:56|~1878~1
- 2 - A 24 OR2 s 0 3 0 1 |ZHANKONG:56|~1878~2
- 3 - A 24 AND2 s 0 2 0 2 |ZHANKONG:56|~1878~3
- 4 - A 17 AND2 s 0 2 0 3 |ZHANKONG:56|~1898~1
- 8 - A 17 OR2 s 0 4 0 1 |ZHANKONG:56|~1926~1
- 5 - A 17 AND2 s ! 0 2 0 1 |ZHANKONG:56|~1950~1
- 6 - A 17 OR2 s 0 3 0 1 |ZHANKONG:56|~1950~2
- 7 - A 17 OR2 s 0 4 0 1 |ZHANKONG:56|~1950~3
- 3 - A 13 AND2 s 0 3 0 1 |ZHANKONG:56|~2376~1
- 3 - A 01 AND2 s 0 3 0 2 |ZHANKONG:56|~2376~2
- 5 - A 13 AND2 s 0 3 0 2 |ZHANKONG:56|~2376~3
- 7 - A 13 OR2 s 0 4 0 1 |ZHANKONG:56|~2376~4
- 1 - A 08 OR2 0 2 0 11 |ZHANKONG:56|:2376
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\vhdl\vhd\plj.rpt
plj
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 40/ 96( 41%) 29/ 48( 60%) 14/ 48( 29%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
B: 10/ 96( 10%) 27/ 48( 56%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 12/ 96( 12%) 2/ 48( 4%) 13/ 48( 27%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\vhd\plj.rpt
plj
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 49 |BASECLK:50|:27
LCELL 28 |CLOCKMUX:10|:46
DFF 18 |FREDEVIDER:25|Temp5
DFF 7 |FREDEVIDER:25|Temp3
DFF 6 |FREDEVIDER:25|Temp2
DFF 6 |FREDEVIDER:25|Temp4
INPUT 5 clkin
INPUT 5 clock
INPUT 3 FCLK
LCELL 1 |CLOCKMUX:10|:40
Device-Specific Information: d:\vhdl\vhd\plj.rpt
plj
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 Reset
INPUT 3 ENABLE
Device-Specific Information: d:\vhdl\vhd\plj.rpt
plj
** EQUATIONS **
clkin : INPUT;
clock : INPUT;
ENABLE : INPUT;
FCLK : INPUT;
Reset : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC8_B5;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC1_A3;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC2_A4;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC5_B3;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC4_A1;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC4_B2;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC2_A2;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC1_B5;
-- Node name is 'Dp1'
-- Equation name is 'Dp1', type is output
Dp1 = _LC1_C20;
-- Node name is 'Dp2'
-- Equation name is 'Dp2', type is output
Dp2 = _LC5_C16;
-- Node name is 'Lowlight'
-- Equation name is 'Lowlight', type is output
Lowlight = _LC2_C20;
-- Node name is 'Overlight'
-- Equation name is 'Overlight', type is output
Overlight = !_LC3_C16;
-- Node name is 'period'
-- Equation name is 'period', type is output
period = _LC6_C16;
-- Node name is 'SPK'
-- Equation name is 'SPK', type is output
SPK = VCC;
-- Node name is '|BASECLK:50|:27'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ001);
_EQ001 = _LC3_C17 & _LC6_C16
# clock & !_LC6_C16;
-- Node name is '|CLOCKMUX:10|:40'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = LCELL( _EQ002);
_EQ002 = !_LC6_C16 & _LC7_C4
# clkin & _LC6_C16;
-- Node name is '|CLOCKMUX:10|:46'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ003);
_EQ003 = _LC3_C17 & _LC6_C16
# clkin & !_LC6_C16;
-- Node name is '|COUNTER:19|:31' = '|COUNTER:19|en'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = DFFE(!_LC3_C4, _LC8_C4, VCC, VCC, VCC);
-- Node name is '|COUNTER:19|:32' = '|COUNTER:19|en1'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE(!_LC3_C4, _LC1_C4, VCC, VCC, VCC);
-- Node name is '|COUNTER:19|~31~1' = '|COUNTER:19|en~1'
-- Equation name is '_LC3_B6', type is buried
-- synthesized logic cell
_LC3_B6 = LCELL( _EQ004);
_EQ004 = _LC2_B2 & _LC3_C4 & !_LC4_B6;
-- Node name is '|COUNTER:19|LPM_ADD_SUB:653|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ005);
_EQ005 = _LC6_B8 & _LC8_B4;
-- Node name is '|COUNTER:19|LPM_ADD_SUB:798|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ006);
_EQ006 = _LC1_B2 & _LC8_B2;
-- Node name is '|COUNTER:19|LPM_ADD_SUB:935|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = LCELL( _EQ007);
_EQ007 = _LC1_B10 & _LC7_B10;
-- Node name is '|COUNTER:19|LPM_ADD_SUB:935|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_B10', type is buried
_LC5_B10 = LCELL( _EQ008);
_EQ008 = !_LC1_B10 & _LC6_B10
# _LC6_B10 & !_LC7_B10
# !_LC4_B10 & _LC6_B10
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