📄 change.rpt
字号:
change
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 8/ 48( 16%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 6/ 96( 6%) 5/ 48( 10%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhd\change.rpt
change
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: d:\vhd\change.rpt
change
** EQUATIONS **
clk : INPUT;
m10 : INPUT;
m11 : INPUT;
m12 : INPUT;
m13 : INPUT;
m20 : INPUT;
m21 : INPUT;
m22 : INPUT;
m23 : INPUT;
m30 : INPUT;
m31 : INPUT;
m32 : INPUT;
m33 : INPUT;
n10 : INPUT;
n11 : INPUT;
n12 : INPUT;
n13 : INPUT;
n20 : INPUT;
n21 : INPUT;
n22 : INPUT;
n23 : INPUT;
n30 : INPUT;
n31 : INPUT;
n32 : INPUT;
n33 : INPUT;
period : INPUT;
-- Node name is 'P10'
-- Equation name is 'P10', type is output
P10 = q10;
-- Node name is 'P11'
-- Equation name is 'P11', type is output
P11 = q11;
-- Node name is 'P12'
-- Equation name is 'P12', type is output
P12 = q12;
-- Node name is 'P13'
-- Equation name is 'P13', type is output
P13 = q13;
-- Node name is 'P20'
-- Equation name is 'P20', type is output
P20 = q20;
-- Node name is 'P21'
-- Equation name is 'P21', type is output
P21 = q21;
-- Node name is 'P22'
-- Equation name is 'P22', type is output
P22 = q22;
-- Node name is 'P23'
-- Equation name is 'P23', type is output
P23 = q23;
-- Node name is 'P30'
-- Equation name is 'P30', type is output
P30 = q30;
-- Node name is 'P31'
-- Equation name is 'P31', type is output
P31 = q31;
-- Node name is 'P32'
-- Equation name is 'P32', type is output
P32 = q32;
-- Node name is 'P33'
-- Equation name is 'P33', type is output
P33 = q33;
-- Node name is ':42' = 'q10'
-- Equation name is 'q10', location is LC2_A13, type is buried.
q10 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = n10 & period
# m10 & !period;
-- Node name is ':41' = 'q11'
-- Equation name is 'q11', location is LC4_A13, type is buried.
q11 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = n11 & period
# m11 & !period;
-- Node name is ':40' = 'q12'
-- Equation name is 'q12', location is LC6_A13, type is buried.
q12 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = n12 & period
# m12 & !period;
-- Node name is ':39' = 'q13'
-- Equation name is 'q13', location is LC7_A13, type is buried.
q13 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = n13 & period
# m13 & !period;
-- Node name is ':46' = 'q20'
-- Equation name is 'q20', location is LC5_A13, type is buried.
q20 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = n20 & period
# m20 & !period;
-- Node name is ':45' = 'q21'
-- Equation name is 'q21', location is LC6_B3, type is buried.
q21 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = n21 & period
# m21 & !period;
-- Node name is ':44' = 'q22'
-- Equation name is 'q22', location is LC8_B3, type is buried.
q22 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = n22 & period
# m22 & !period;
-- Node name is ':43' = 'q23'
-- Equation name is 'q23', location is LC3_A13, type is buried.
q23 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = n23 & period
# m23 & !period;
-- Node name is ':50' = 'q30'
-- Equation name is 'q30', location is LC8_A13, type is buried.
q30 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = n30 & period
# m30 & !period;
-- Node name is ':49' = 'q31'
-- Equation name is 'q31', location is LC1_A13, type is buried.
q31 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = n31 & period
# m31 & !period;
-- Node name is ':48' = 'q32'
-- Equation name is 'q32', location is LC1_B3, type is buried.
q32 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = n32 & period
# m32 & !period;
-- Node name is ':47' = 'q33'
-- Equation name is 'q33', location is LC2_B3, type is buried.
q33 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = n33 & period
# m33 & !period;
Project Information d:\vhd\change.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 31,148K
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