counter.rpt

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_LC5_C15 = DFFE( _EQ023, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ023 =  _LC3_C21 &  _LC5_C15
         #  _LC4_C13 &  _LC5_C15
         # !_LC3_C21 & !_LC4_C13 &  num22;

-- Node name is ':15' 
-- Equation name is '_LC1_C19', type is buried 
_LC1_C19 = DFFE( _EQ024, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ024 =  _LC1_C19 &  _LC3_C21
         #  _LC1_C19 &  _LC4_C13
         # !_LC3_C21 & !_LC4_C13 &  num21;

-- Node name is ':17' 
-- Equation name is '_LC3_C19', type is buried 
_LC3_C19 = DFFE( _EQ025, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ025 =  _LC3_C19 &  _LC3_C21
         #  _LC3_C19 &  _LC4_C13
         # !_LC3_C21 & !_LC4_C13 &  num20;

-- Node name is ':19' 
-- Equation name is '_LC7_C19', type is buried 
_LC7_C19 = DFFE( _EQ026, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ026 =  _LC3_C21 &  _LC7_C19
         #  _LC4_C13 &  _LC7_C19
         # !_LC3_C21 &  num33;

-- Node name is ':21' 
-- Equation name is '_LC1_C24', type is buried 
_LC1_C24 = DFFE( _EQ027, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ027 =  _LC1_C24 &  _LC3_C21
         #  _LC1_C24 &  _LC4_C13
         # !_LC3_C21 &  num32;

-- Node name is ':23' 
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = DFFE( _EQ028, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ028 =  _LC2_C13 &  _LC3_C21
         #  _LC2_C13 &  _LC4_C13
         # !_LC3_C21 &  num31;

-- Node name is ':25' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = DFFE( _EQ029, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ029 =  _LC3_C21 &  _LC4_C19
         #  _LC4_C13 &  _LC4_C19
         # !_LC3_C21 &  num30;

-- Node name is ':27' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = DFFE( _EQ030, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ030 =  en &  en1 &  overmode
         #  en & !en1 &  _LC5_C21;

-- Node name is ':29' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = DFFE( _EQ031, GLOBAL( clk2),  VCC,  VCC,  VCC);
  _EQ031 =  en &  _LC7_C21
         #  en & !en1 &  _LC1_C21;

-- Node name is ':135' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = LCELL( _EQ032);
  _EQ032 = !num30 & !num31 & !num32 & !num33;

-- Node name is ':474' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = LCELL( _EQ033);
  _EQ033 =  en1 &  _LC4_C13 & !overmode;

-- Node name is '~600~1' 
-- Equation name is '~600~1', location is LC2_C23, type is buried.
-- synthesized logic cell 
_LC2_C23 = LCELL( _EQ034);
  _EQ034 = !en & !_LC1_C22;

-- Node name is ':600' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ035);
  _EQ035 =  num10 & !num11 & !num12 &  num13;

-- Node name is ':614' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ036);
  _EQ036 =  num20 & !num21 & !num22 &  num23;

-- Node name is ':628' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ037);
  _EQ037 =  num30 & !num31 & !num32 &  num33;

-- Node name is ':692' 
-- Equation name is '_LC3_C13', type is buried 
_LC3_C13 = LCELL( _EQ038);
  _EQ038 = !num32 &  num33
         # !_LC6_C13 &  num33
         #  _LC6_C13 &  num32 & !num33
         #  _LC5_C13;

-- Node name is ':835' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ039);
  _EQ039 = !_LC5_C13 & !_LC6_C13 &  num32
         #  _LC2_C15 & !_LC5_C13 &  _LC6_C13 & !num32
         # !_LC2_C15 &  num32;

-- Node name is ':842' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = LCELL( _EQ040);
  _EQ040 =  _LC2_C15 & !_LC5_C13 & !num30 &  num31
         #  _LC2_C15 & !_LC5_C13 &  num30 & !num31;

-- Node name is ':854' 
-- Equation name is '_LC8_C14', type is buried 
_LC8_C14 = LCELL( _EQ041);
  _EQ041 =  _LC2_C15 &  _LC5_C13;

-- Node name is ':855' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ042);
  _EQ042 = !_LC2_C15 & !num22 &  num23
         # !_LC2_C15 & !_LC8_C19 &  num23
         # !_LC2_C15 &  _LC8_C19 &  num22 & !num23;

-- Node name is ':958' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = LCELL( _EQ043);
  _EQ043 =  _LC1_C22 &  _LC2_C15 &  _LC3_C13
         # !_LC2_C15 &  num33
         # !_LC1_C22 &  num33;

-- Node name is ':964' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ044);
  _EQ044 =  _LC1_C22 &  _LC2_C22
         # !_LC1_C22 &  num32;

-- Node name is ':970' 
-- Equation name is '_LC7_C13', type is buried 
_LC7_C13 = LCELL( _EQ045);
  _EQ045 =  _LC1_C13 &  _LC1_C22
         # !_LC2_C15 &  num31
         # !_LC1_C22 &  num31;

-- Node name is ':982' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ046);
  _EQ046 =  _LC1_C22 &  _LC4_C15
         #  _LC1_C22 &  _LC8_C14
         # !_LC1_C22 &  num23;

-- Node name is ':988' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ047);
  _EQ047 = !_LC2_C15 & !_LC8_C19 &  num22
         #  _LC1_C22 & !_LC2_C15 &  _LC8_C19 & !num22
         # !_LC1_C22 &  num22;

-- Node name is ':994' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ048);
  _EQ048 = !_LC2_C15 & !num20 &  num21
         #  _LC1_C22 & !_LC2_C15 &  num20 & !num21
         # !_LC1_C22 &  num21;

-- Node name is ':1006' 
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = LCELL( _EQ049);
  _EQ049 =  _LC1_C22 &  _LC2_C15 &  _LC5_C13
         # !_LC1_C22 &  _LC5_C22;

-- Node name is ':1007' 
-- Equation name is '_LC2_C18', type is buried 
_LC2_C18 = LCELL( _EQ050);
  _EQ050 =  _LC1_C22 &  _LC8_C14;

-- Node name is '~1130~1' 
-- Equation name is '~1130~1', location is LC3_C21, type is buried.
-- synthesized logic cell 
!_LC3_C21 = _LC3_C21~NOT;
_LC3_C21~NOT = LCELL( _EQ051);
  _EQ051 =  en &  en1 & !overmode;

-- Node name is '~1196~1' 
-- Equation name is '~1196~1', location is LC7_C14, type is buried.
-- synthesized logic cell 
_LC7_C14 = LCELL( _EQ052);
  _EQ052 = !en &  _LC1_C22 & !num20
         # !en &  _LC1_C22 &  _LC8_C14;

-- Node name is '~1203~1' 
-- Equation name is '~1203~1', location is LC2_C21, type is buried.
-- synthesized logic cell 
_LC2_C21 = LCELL( _EQ053);
  _EQ053 =  en & !en1;

-- Node name is '~1220~1' 
-- Equation name is '~1220~1', location is LC2_C14, type is buried.
-- synthesized logic cell 
!_LC2_C14 = _LC2_C14~NOT;
_LC2_C14~NOT = LCELL( _EQ054);
  _EQ054 =  _LC1_C22 &  _LC2_C15;

-- Node name is '~1220~2' 
-- Equation name is '~1220~2', location is LC3_C14, type is buried.
-- synthesized logic cell 
_LC3_C14 = LCELL( _EQ055);
  _EQ055 = !en & !num30
         # !en &  _LC5_C13;

-- Node name is '~1220~3' 
-- Equation name is '~1220~3', location is LC5_C14, type is buried.
-- synthesized logic cell 
_LC5_C14 = LCELL( _EQ056);
  _EQ056 = !en & !_LC1_C22
         # !en & !_LC2_C15
         #  _LC2_C21;



Project Information                                         d:\vhd\counter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:03
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:09


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,471K