clockmux.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;

entity ClockMux is
port
( clkina,clkinb:in std_logic;
  period:in std_logic;
  clkouta,clkoutb:out std_logic
);
end;

architecture a of ClockMux is
signal m1,m2:std_logic;
begin
  process(period,clkina,clkinb)
    begin
      if period='1' then
        m1<=clkinb;
        m2<=clkina;
      else 
        m1<=clkina;
        m2<=clkinb;
      end if;
   end process;
     
     clkouta<=m1;
     clkoutb<=m2;
 end a;