statemachine.rpt

本频率计具有测周、测频、测量占空比等基本功能

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Device-Specific Information:                  f:\maxplus2\vhd\statemachine.rpt
statemachine

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        9         clock100kHz


Device-Specific Information:                  f:\maxplus2\vhd\statemachine.rpt
statemachine

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        8         reset


Device-Specific Information:                  f:\maxplus2\vhd\statemachine.rpt
statemachine

** EQUATIONS **

clock1kHz : INPUT;
clock10Hz : INPUT;
clock10kHz : INPUT;
clock100Hz : INPUT;
clock100kHz : INPUT;
low      : INPUT;
over     : INPUT;
reset    : INPUT;

-- Node name is 'dp1' 
-- Equation name is 'dp1', type is output 
dp1      =  _LC1_B14;

-- Node name is 'dp2' 
-- Equation name is 'dp2', type is output 
dp2      =  _LC8_B14;

-- Node name is 'en' 
-- Equation name is 'en', type is output 
en       =  _LC7_B14;

-- Node name is 'lowlight' 
-- Equation name is 'lowlight', type is output 
lowlight =  _LC3_B23;

-- Node name is 'outclk' 
-- Equation name is 'outclk', type is output 
outclk   =  _LC4_B17;

-- Node name is 'overlight' 
-- Equation name is 'overlight', type is output 
overlight =  _LC2_B22;

-- Node name is 'over~1' 
-- Equation name is 'over~1', location is LC7_B22, type is buried.
-- synthesized logic cell 
_LC7_B22 = LCELL( _EQ001);
  _EQ001 = !over &  state~3;

-- Node name is 'period' 
-- Equation name is 'period', type is output 
period   =  _LC6_B14;

-- Node name is 'state~1' 
-- Equation name is 'state~1', location is LC4_B22, type is buried.
state~1  = DFFE( _EQ002, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ002 =  over &  state~3
         # !low &  over &  state~1;

-- Node name is 'state~2' 
-- Equation name is 'state~2', location is LC2_B23, type is buried.
state~2  = DFFE( _EQ003, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ003 =  over &  state~8
         # !low &  over &  state~2;

-- Node name is 'state~3' 
-- Equation name is 'state~3', location is LC3_B22, type is buried.
state~3  = DFFE( _EQ004, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ004 =  _LC8_B22 & !low & !over
         #  over &  state~4;

-- Node name is 'state~4' 
-- Equation name is 'state~4', location is LC1_B22, type is buried.
state~4  = DFFE( _EQ005, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ005 =  _LC6_B22
         #  _LC7_B22 &  low
         #  low &  state~1;

-- Node name is 'state~5' 
-- Equation name is 'state~5', location is LC5_B22, type is buried.
state~5  = DFFE( _EQ006, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ006 = !low & !over &  state~5
         #  _LC1_B17 &  low & !over;

-- Node name is 'state~6' 
-- Equation name is 'state~6', location is LC1_B23, type is buried.
state~6  = DFFE( _EQ007, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ007 =  _LC4_B14 &  low
         # !low &  state~6
         #  over;

-- Node name is 'state~7' 
-- Equation name is 'state~7', location is LC5_B23, type is buried.
state~7  = DFFE( _EQ008, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ008 =  _LC6_B23 & !over
         #  over & !state~6
         #  _LC7_B23;

-- Node name is 'state~8' 
-- Equation name is 'state~8', location is LC4_B23, type is buried.
state~8  = DFFE( _EQ009, GLOBAL( clock100kHz), GLOBAL(!reset),  VCC,  VCC);
  _EQ009 =  _LC8_B23 & !low & !over
         #  over &  state~7;

-- Node name is '~224~1' 
-- Equation name is '~224~1', location is LC4_B14, type is buried.
-- synthesized logic cell 
_LC4_B14 = LCELL( _EQ010);
  _EQ010 = !state~5 & !state~7;

-- Node name is '~230~1' 
-- Equation name is '~230~1', location is LC1_B17, type is buried.
-- synthesized logic cell 
_LC1_B17 = LCELL( _EQ011);
  _EQ011 =  state~4
         # !state~6;

-- Node name is '~242~1' 
-- Equation name is '~242~1', location is LC8_B23, type is buried.
-- synthesized logic cell 
_LC8_B23 = LCELL( _EQ012);
  _EQ012 =  state~8
         #  state~2;

-- Node name is ':243' 
-- Equation name is '_LC7_B23', type is buried 
_LC7_B23 = LCELL( _EQ013);
  _EQ013 =  low &  state~2;

-- Node name is '~244~1' 
-- Equation name is '~244~1', location is LC6_B23, type is buried.
-- synthesized logic cell 
_LC6_B23 = LCELL( _EQ014);
  _EQ014 =  low &  state~8
         # !low &  state~7;

-- Node name is '~248~1' 
-- Equation name is '~248~1', location is LC6_B22, type is buried.
-- synthesized logic cell 
_LC6_B22 = LCELL( _EQ015);
  _EQ015 = !low & !over &  state~4
         #  over &  state~5;

-- Node name is '~250~1' 
-- Equation name is '~250~1', location is LC8_B22, type is buried.
-- synthesized logic cell 
_LC8_B22 = LCELL( _EQ016);
  _EQ016 =  state~3
         #  state~1;

-- Node name is ':484' 
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = LCELL( _EQ017);
  _EQ017 = !_LC4_B14
         #  state~3
         #  _LC1_B17
         #  state~8;

-- Node name is '~496~1' 
-- Equation name is '~496~1', location is LC3_B17, type is buried.
-- synthesized logic cell 
_LC3_B17 = LCELL( _EQ018);
  _EQ018 =  clock10kHz &  state~4
         #  clock1kHz & !state~4;

-- Node name is '~499~1' 
-- Equation name is '~499~1', location is LC5_B17, type is buried.
-- synthesized logic cell 
_LC5_B17 = LCELL( _EQ019);
  _EQ019 =  _LC3_B17 & !state~5
         #  clock100kHz &  state~5;

-- Node name is '~502~1' 
-- Equation name is '~502~1', location is LC6_B17, type is buried.
-- synthesized logic cell 
_LC6_B17 = LCELL( _EQ020);
  _EQ020 =  _LC5_B17 &  state~6
         #  clock10Hz & !state~6;

-- Node name is '~505~1' 
-- Equation name is '~505~1', location is LC7_B17, type is buried.
-- synthesized logic cell 
_LC7_B17 = LCELL( _EQ021);
  _EQ021 =  _LC6_B17 & !state~7
         #  clock100Hz &  state~7;

-- Node name is '~508~1' 
-- Equation name is '~508~1', location is LC4_B17, type is buried.
-- synthesized logic cell 
_LC4_B17 = LCELL( _EQ022);
  _EQ022 =  _LC7_B17 & !state~8
         #  clock1kHz &  state~8;

-- Node name is ':534' 
-- Equation name is '_LC2_B22', type is buried 
_LC2_B22 = LCELL( _EQ023);
  _EQ023 = !_LC1_B17 &  state~2 & !state~3 & !state~5;

-- Node name is ':558' 
-- Equation name is '_LC3_B23', type is buried 
_LC3_B23 = LCELL( _EQ024);
  _EQ024 = !_LC1_B17 &  _LC4_B14 & !_LC8_B23 & !state~3;

-- Node name is ':571' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ025);
  _EQ025 = !state~2
         #  state~3
         #  state~5
         #  state~4;

-- Node name is ':582' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ026);
  _EQ026 =  _LC5_B14 &  state~6 & !state~7 & !state~8;

-- Node name is ':600' 
-- Equation name is '_LC3_B14', type is buried 
_LC3_B14 = LCELL( _EQ027);
  _EQ027 =  _LC1_B14 & !state~4 & !state~5
         #  state~3 & !state~4 & !state~5;

-- Node name is ':604' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = LCELL( _EQ028);
  _EQ028 =  _LC3_B14 & !state~7 & !state~8
         # !state~6 & !state~7 & !state~8;

-- Node name is ':616' 
-- Equation name is '_LC2_B17', type is buried 
_LC2_B17 = LCELL( _EQ029);
  _EQ029 =  _LC8_B14 & !state~3
         #  state~4;

-- Node name is ':627' 
-- Equation name is '_LC2_B14', type is buried 
_LC2_B14 = LCELL( _EQ030);
  _EQ030 =  _LC2_B17 & !state~5 &  state~6;

-- Node name is ':628' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = LCELL( _EQ031);
  _EQ031 =  _LC2_B14 & !state~8
         #  state~7 & !state~8;



Project Information                           f:\maxplus2\vhd\statemachine.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,328K