fenpin_10.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;

entity Fenpin_10 is
port
( clkin:in std_logic;
  clkout:out std_logic
);

end;

architecture a of Fenpin_10 is
constant N:integer:=4;
signal counter:integer range 0 to N;
signal clk:Std_logic;
begin
   process(clkin)
    begin
     if rising_edge(clkin) then
       if counter=N then
         counter<=0;
         clk<=not clk;
       else
         counter<=counter+1;
       end if;
     end if;
    end process;
   clkout<=clk;
end a;