📄 led.rpt
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Device-Specific Information: d:\vhd\led.rpt
led
** EQUATIONS **
En : INPUT;
Numin0 : INPUT;
Numin1 : INPUT;
Numin2 : INPUT;
Numin3 : INPUT;
-- Node name is 'Numout0'
-- Equation name is 'Numout0', type is output
Numout0 = _LC6_A17;
-- Node name is 'Numout1'
-- Equation name is 'Numout1', type is output
Numout1 = _LC1_A13;
-- Node name is 'Numout2'
-- Equation name is 'Numout2', type is output
Numout2 = _LC3_A13;
-- Node name is 'Numout3'
-- Equation name is 'Numout3', type is output
Numout3 = _LC4_A17;
-- Node name is 'Numout4'
-- Equation name is 'Numout4', type is output
Numout4 = _LC8_A17;
-- Node name is 'Numout5'
-- Equation name is 'Numout5', type is output
Numout5 = _LC1_A17;
-- Node name is 'Numout6'
-- Equation name is 'Numout6', type is output
Numout6 = _LC5_A17;
-- Node name is ':262'
-- Equation name is '_LC4_A14', type is buried
!_LC4_A14 = _LC4_A14~NOT;
_LC4_A14~NOT = LCELL( _EQ001);
_EQ001 = _LC7_A14
# !Numin1
# !Numin2;
-- Node name is '~286~1'
-- Equation name is '~286~1', location is LC7_A14, type is buried.
-- synthesized logic cell
_LC7_A14 = LCELL( _EQ002);
_EQ002 = Numin3
# !Numin0;
-- Node name is '~298~1'
-- Equation name is '~298~1', location is LC5_A13, type is buried.
-- synthesized logic cell
_LC5_A13 = LCELL( _EQ003);
_EQ003 = Numin3
# Numin0;
-- Node name is ':298'
-- Equation name is '_LC7_A13', type is buried
!_LC7_A13 = _LC7_A13~NOT;
_LC7_A13~NOT = LCELL( _EQ004);
_EQ004 = Numin1
# !Numin2
# _LC5_A13;
-- Node name is ':325'
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = LCELL( _EQ005);
_EQ005 = !Numin2
# _LC5_A13;
-- Node name is ':334'
-- Equation name is '_LC2_A14', type is buried
!_LC2_A14 = _LC2_A14~NOT;
_LC2_A14~NOT = LCELL( _EQ006);
_EQ006 = _LC7_A14
# Numin1
# Numin2;
-- Node name is ':346'
-- Equation name is '_LC2_A17', type is buried
!_LC2_A17 = _LC2_A17~NOT;
_LC2_A17~NOT = LCELL( _EQ007);
_EQ007 = _LC5_A13
# Numin1
# Numin2;
-- Node name is '~379~1'
-- Equation name is '~379~1', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ008);
_EQ008 = !Numin2
# Numin3
# Numin0 & Numin1
# !Numin0 & !Numin1;
-- Node name is ':424'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ009);
_EQ009 = !Numin0 & Numin1 & Numin2 & !Numin3
# Numin0 & !Numin1 & Numin2 & !Numin3
# !Numin0 & !Numin1 & !Numin2 & Numin3;
-- Node name is ':433'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ010);
_EQ010 = _LC6_A13 & !_LC7_A13
# !_LC4_A13;
-- Node name is ':463'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ011);
_EQ011 = !Numin0 & !Numin1 & !Numin2 & Numin3
# !Numin0 & Numin1 & !Numin3;
-- Node name is '~501~1'
-- Equation name is '~501~1', location is LC4_A13, type is buried.
-- synthesized logic cell
_LC4_A13 = LCELL( _EQ012);
_EQ012 = !Numin1
# Numin2
# _LC5_A13 & _LC7_A14;
-- Node name is ':501'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = LCELL( _EQ013);
_EQ013 = !_LC2_A14 & _LC4_A13 & !_LC4_A14;
-- Node name is ':563'
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = LCELL( _EQ014);
_EQ014 = En & !_LC2_A14 & _LC7_A17
# En & _LC2_A17;
-- Node name is ':569'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ015);
_EQ015 = En & _LC8_A13
# En & !_LC4_A13
# En & _LC7_A13;
-- Node name is ':575'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ016);
_EQ016 = En & _LC5_A13
# En & !Numin1
# En & Numin2;
-- Node name is ':581'
-- Equation name is '_LC4_A17', type is buried
_LC4_A17 = LCELL( _EQ017);
_EQ017 = En & _LC2_A13 & !_LC2_A14
# En & _LC2_A17;
-- Node name is ':587'
-- Equation name is '_LC8_A17', type is buried
_LC8_A17 = LCELL( _EQ018);
_EQ018 = En & _LC1_A14 & !_LC2_A14
# En & _LC2_A17;
-- Node name is ':593'
-- Equation name is '_LC1_A17', type is buried
_LC1_A17 = LCELL( _EQ019);
_EQ019 = En & _LC3_A17
# En & _LC2_A17;
-- Node name is ':599'
-- Equation name is '_LC5_A17', type is buried
_LC5_A17 = LCELL( _EQ020);
_EQ020 = En & !_LC2_A14 & !_LC2_A17 & !_LC4_A14;
Project Information d:\vhd\led.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,441K
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