statemachine.vhd

来自「本频率计具有测周、测频、测量占空比等基本功能」· VHDL 代码 · 共 163 行

library ieee;
use ieee.std_logic_1164.all;

entity Statemachine is
port
(
 clock10Hz,clock100Hz,clock1kHz,clock10kHz,clock100kHz:in std_logic;
 low,over:in std_logic;
 reset:in std_logic;
 en:out std_logic;
 dp1,dp2:out std_logic;
 overlight,lowlight:out std_logic;
 period:out std_logic;
 outclk:out std_logic
);
end;

architecture a of Statemachine is
type state_type is (F1M,F100k,F10k,P1ms,P10ms,P100ms,overerr,lowerr);
signal state:state_type;
begin
  process(clock100kHz,reset)
  begin
    if(reset='1') then
      state<=F10k;
    elsif rising_edge(clock100kHz) then
      case state is
      when F1M=>
        if over='1' then
          state<=overerr;
        elsif low='1' then
          state<=F100k;
        else
          state<=F1M;
        end if;
      when F100k=>
        if over='1' then
          state<=F1M;
        elsif low='1' then
          state<=F10k;
        else
          state<=F100k;
        end if;
      when F10k=>
        if over='1' then
          state<=F100k;
        elsif low='1' then
          state<=P1ms;
        else
          state<=F10k;
        end if;
      when P1ms=>
        if over='1' then
          state<=P10ms;
        elsif low='1' then
          state<=F10k;
        else
          state<=P1ms;
        end if;
      when P10ms=>
        if over='1' then
          state<=P100ms;
        elsif low='1' then
          state<=P1ms;
        else
          state<=P10ms;
        end if;
      when P100ms=>
        if over='1' then
          state<=lowerr;
        elsif low='1' then
          state<=P10ms;
        else
          state<=P100ms;
        end if;
      when overerr=>
        if low='1' then
          state<=F100k;
        elsif over='1' then
          state<=overerr;
        else
          state<=F1M;
        end if;
      when lowerr=>
        if low='1' then
          state<=P10ms;
        elsif over='1' then
          state<=lowerr;
        else
          state<=P100ms;
        end if;
       end case;
      end if;
     end process;

     process(state)
       begin
        case state is
          when F1M=>
            en<='1';
            outclk<=clock1kHz;
            overlight<='0';
            lowlight<='0';
            period<='0';
            dp1<='0';
            dp2<='0';
          when F100k=>
            en<='1';
            outclk<=clock100Hz;
            overlight<='0';
            lowlight<='0';
            period<='0';
            dp1<='0';
            dp2<='1';
          when F10k=>
            en<='1';
            outclk<=clock10Hz;
            overlight<='0';
            lowlight<='0';
            period<='0';
            dp1<='1';
            dp2<='0';
          when P1ms=>
            en<='1';
            outclk<=clock100kHz;
            overlight<='0';
            lowlight<='0';
            period<='1';
            dp1<='0';
            dp2<='0';
          when P10ms=>
            en<='1';
            outclk<=clock10kHz;
            overlight<='0';
            lowlight<='0';
            period<='1';
            dp1<='0';
            dp2<='1';
          when P100ms=>
            en<='1';
            outclk<=clock1kHz;
            overlight<='0';
            lowlight<='0';
            period<='1';
            dp1<='1';
            dp2<='0';
          when overerr=>
            en<='0';
            outclk<=clock1kHz;
            overlight<='1';
            lowlight<='0';
            period<='0';
          when lowerr=>
            en<='0';
            outclk<=clock1kHz;
            overlight<='0';
            lowlight<='1';
            period<='1';
 
         end case;
       end process;
      end a;