zhankong.rpt

本频率计具有测周、测频、测量占空比等基本功能

-- Node name is ':1084' 
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = LCELL( _EQ070);
  _EQ070 = !_LC4_B17 & !_LC8_B17 &  Totalnum22
         #  _LC1_B16 &  _LC4_B17 & !_LC8_B17 & !Totalnum22
         # !_LC1_B16 &  Totalnum22;

-- Node name is ':1090' 
-- Equation name is '_LC5_B17', type is buried 
_LC5_B17 = LCELL( _EQ071);
  _EQ071 = !_LC8_B17 & !Totalnum20 &  Totalnum21
         #  _LC1_B16 & !_LC8_B17 &  Totalnum20 & !Totalnum21
         # !_LC1_B16 &  Totalnum21;

-- Node name is ':1102' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ072);
  _EQ072 = !_LC1_B16 &  _LC7_B16
         #  _LC1_B16 &  _LC3_B22 &  _LC8_B17;

-- Node name is ':1103' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ073);
  _EQ073 =  _LC1_B16 &  _LC3_B22 &  _LC8_B17;

-- Node name is ':1133' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = LCELL( _EQ074);
  _EQ074 =  Highnum10 & !Highnum11 & !Highnum12 &  Highnum13;

-- Node name is ':1147' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = LCELL( _EQ075);
  _EQ075 =  Highnum20 & !Highnum21 & !Highnum22 &  Highnum23;

-- Node name is ':1161' 
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ076);
  _EQ076 =  Highnum30 & !Highnum31 & !Highnum32 &  Highnum33;

-- Node name is ':1373' 
-- Equation name is '_LC5_B6', type is buried 
_LC5_B6  = LCELL( _EQ077);
  _EQ077 =  _LC2_B9 &  _LC6_B6
         #  _LC4_B6 & !_LC6_B6;

-- Node name is ':1374' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ078);
  _EQ078 =  _LC2_B9 &  _LC6_B6;

-- Node name is ':1499' 
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ079);
  _EQ079 =  Highnum22 & !_LC4_B4 & !_LC6_B6
         # !Highnum22 &  _LC4_B4 &  _LC5_B5 & !_LC6_B6
         #  Highnum22 & !_LC5_B5;

-- Node name is ':1506' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = LCELL( _EQ080);
  _EQ080 = !Highnum20 &  Highnum21 &  _LC5_B5 & !_LC6_B6
         #  Highnum20 & !Highnum21 &  _LC5_B5 & !_LC6_B6;

-- Node name is ':1518' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ081);
  _EQ081 =  _LC2_B9 &  _LC5_B5 &  _LC6_B6;

-- Node name is ':1519' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ082);
  _EQ082 = !Highnum12 &  Highnum13 & !_LC5_B5
         #  Highnum13 & !_LC3_B1 & !_LC5_B5
         #  Highnum12 & !Highnum13 &  _LC3_B1 & !_LC5_B5;

-- Node name is ':1583' 
-- Equation name is '_LC7_B6', type is buried 
_LC7_B6  = LCELL( _EQ083);
  _EQ083 =  _LC5_B5 &  _LC5_B6 &  _LC7_B8
         #  Highnum23 & !_LC5_B5
         #  Highnum23 & !_LC7_B8;

-- Node name is ':1589' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = LCELL( _EQ084);
  _EQ084 =  _LC5_B4 &  _LC7_B8
         #  Highnum22 & !_LC7_B8;

-- Node name is ':1595' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = LCELL( _EQ085);
  _EQ085 =  _LC1_B6 &  _LC7_B8
         #  Highnum21 & !_LC5_B5
         #  Highnum21 & !_LC7_B8;

-- Node name is ':1607' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ086);
  _EQ086 =  _LC6_B5 &  _LC7_B8
         #  _LC4_B5 &  _LC7_B8
         #  Highnum13 & !_LC7_B8;

-- Node name is ':1613' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ087);
  _EQ087 =  Highnum12 & !_LC3_B1 & !_LC5_B5
         # !Highnum12 &  _LC3_B1 & !_LC5_B5 &  _LC7_B8
         #  Highnum12 & !_LC7_B8;

-- Node name is ':1619' 
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = LCELL( _EQ088);
  _EQ088 = !Highnum10 &  Highnum11 & !_LC5_B5
         #  Highnum10 & !Highnum11 & !_LC5_B5 &  _LC7_B8
         #  Highnum11 & !_LC7_B8;

-- Node name is '~1819~1' 
-- Equation name is '~1819~1', location is LC2_B17, type is buried.
-- synthesized logic cell 
_LC2_B17 = LCELL( _EQ089);
  _EQ089 =  En & !Entransfer;

-- Node name is '~1830~1' 
-- Equation name is '~1830~1', location is LC1_B1, type is buried.
-- synthesized logic cell 
_LC1_B1  = LCELL( _EQ090);
  _EQ090 = !En &  _LC7_B8;

-- Node name is '~1830~2' 
-- Equation name is '~1830~2', location is LC4_B1, type is buried.
-- synthesized logic cell 
_LC4_B1  = LCELL( _EQ091);
  _EQ091 =  En & !Entransfer
         # !En & !_LC7_B8;

-- Node name is '~1854~1' 
-- Equation name is '~1854~1', location is LC3_B8, type is buried.
-- synthesized logic cell 
_LC3_B8  = LCELL( _EQ092);
  _EQ092 = !En &  _LC5_B5 &  _LC7_B8;

-- Node name is '~1854~2' 
-- Equation name is '~1854~2', location is LC3_B4, type is buried.
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ093);
  _EQ093 =  En & !Entransfer
         # !En & !_LC5_B5
         # !En & !_LC7_B8;

-- Node name is '~1860~1' 
-- Equation name is '~1860~1', location is LC5_B9, type is buried.
-- synthesized logic cell 
!_LC5_B9 = _LC5_B9~NOT;
_LC5_B9~NOT = LCELL( _EQ094);
  _EQ094 =  Highnum30 &  Highnum31 &  Highnum32;

-- Node name is '~1860~2' 
-- Equation name is '~1860~2', location is LC6_B9, type is buried.
-- synthesized logic cell 
_LC6_B9  = LCELL( _EQ095);
  _EQ095 =  En & !Entransfer
         # !En &  _LC5_B9
         # !En &  _LC5_B8;

-- Node name is '~1860~3' 
-- Equation name is '~1860~3', location is LC7_B9, type is buried.
-- synthesized logic cell 
_LC7_B9  = LCELL( _EQ096);
  _EQ096 = !Highnum33 & !_LC5_B9
         #  _LC2_B9;

-- Node name is '~1866~1' 
-- Equation name is '~1866~1', location is LC8_B7, type is buried.
-- synthesized logic cell 
_LC8_B7  = LCELL( _EQ097);
  _EQ097 =  En & !Entransfer
         # !En &  _LC7_B7
         # !En &  _LC5_B8;

-- Node name is '~1872~1' 
-- Equation name is '~1872~1', location is LC3_B7, type is buried.
-- synthesized logic cell 
_LC3_B7  = LCELL( _EQ098);
  _EQ098 =  En & !Entransfer
         # !En &  _LC2_B7
         # !En &  _LC5_B8;

-- Node name is '~1878~1' 
-- Equation name is '~1878~1', location is LC5_B8, type is buried.
-- synthesized logic cell 
!_LC5_B8 = _LC5_B8~NOT;
_LC5_B8~NOT = LCELL( _EQ099);
  _EQ099 =  _LC5_B5 &  _LC6_B6 &  _LC7_B8;

-- Node name is '~1878~2' 
-- Equation name is '~1878~2', location is LC4_B9, type is buried.
-- synthesized logic cell 
_LC4_B9  = LCELL( _EQ100);
  _EQ100 =  En & !Entransfer
         # !En &  _LC5_B8;

-- Node name is '~1878~3' 
-- Equation name is '~1878~3', location is LC4_B8, type is buried.
-- synthesized logic cell 
_LC4_B8  = LCELL( _EQ101);
  _EQ101 = !En & !_LC5_B8;

-- Node name is '~1926~1' 
-- Equation name is '~1926~1', location is LC2_B24, type is buried.
-- synthesized logic cell 
_LC2_B24 = LCELL( _EQ102);
  _EQ102 = !En &  _LC1_B16 & !Totalnum20
         # !En &  _LC1_B16 &  _LC1_B24;

-- Node name is '~1950~1' 
-- Equation name is '~1950~1', location is LC4_B18, type is buried.
-- synthesized logic cell 
!_LC4_B18 = _LC4_B18~NOT;
_LC4_B18~NOT = LCELL( _EQ103);
  _EQ103 =  _LC1_B16 &  _LC8_B17;

-- Node name is '~1950~2' 
-- Equation name is '~1950~2', location is LC5_B18, type is buried.
-- synthesized logic cell 
_LC5_B18 = LCELL( _EQ104);
  _EQ104 = !En & !Totalnum30
         # !En &  _LC3_B22;

-- Node name is '~1950~3' 
-- Equation name is '~1950~3', location is LC6_B18, type is buried.
-- synthesized logic cell 
_LC6_B18 = LCELL( _EQ105);
  _EQ105 =  _LC2_B17
         # !En & !_LC1_B16
         # !En & !_LC8_B17;

-- Node name is '~2376~1' 
-- Equation name is '~2376~1', location is LC2_B7, type is buried.
-- synthesized logic cell 
_LC2_B7  = LCELL( _EQ106);
  _EQ106 = !Highnum30 & !_LC2_B9 &  _LC6_B6;

-- Node name is '~2376~2' 
-- Equation name is '~2376~2', location is LC4_B7, type is buried.
-- synthesized logic cell 
_LC4_B7  = LCELL( _EQ107);
  _EQ107 = !_LC2_B9 &  _LC3_B8 &  _LC6_B6;

-- Node name is '~2376~3' 
-- Equation name is '~2376~3', location is LC7_B7, type is buried.
-- synthesized logic cell 
_LC7_B7  = LCELL( _EQ108);
  _EQ108 = !Highnum31 & !_LC2_B9 &  _LC6_B6
         # !Highnum30 & !_LC2_B9 &  _LC6_B6;

-- Node name is ':2376' 
-- Equation name is '_LC7_B8', type is buried 
_LC7_B8  = LCELL( _EQ109);
  _EQ109 =  m & !n
         # !m &  n;



Project Information                                   d:\vhdl\vhd\zhankong.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:02
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 38,217K