adder_cs.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.ISCAS.all;

entity adder_CS is
    Port ( a : 	in 	std_logic_vector(15 downto 0);
           b : 	in 	std_logic_vector(15 downto 0);
           Cin : 	in 	std_logic;
           sum : 	out 	std_logic_vector(15 downto 0);
           Cout : out 	std_logic);
end adder_CS;

architecture behavioral of adder_CS is

begin

process(a,b,Cin)
variable temp_sum : std_logic_vector(sum'range);
variable temp_Cout: std_logic;
constant groupa: iarray(0 to 2) := (4,5,7);

begin 
carry_select_adder(groupa, a, b, Cin, temp_sum, temp_Cout);
sum <= not temp_sum;
Cout <= not temp_Cout;

end process; 

end behavioral;