rom256x16.edn

含有各类寄存器

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 8 15 11 13 7)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i; Cores Update # 3"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_sinit_value = 0 ")
       (comment "c_has_en = 1 ")
       (comment "c_reg_inputs = 0 ")
       (comment "c_yclk_is_rising = 1 ")
       (comment "c_ysinit_is_high = 1 ")
       (comment "c_ywe_is_high = 1 ")
       (comment "c_yprimitive_type = 4kx1 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_has_rdy = 0 ")
       (comment "c_write_mode = 0 ")
       (comment "c_width = 16 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_nd = 0 ")
       (comment "c_has_we = 0 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_has_rfd = 0 ")
       (comment "c_has_din = 0 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_yen_is_high = 1 ")
       (comment "c_family = virtex ")
       (comment "InstanceName = rom256x16 ")
       (comment "c_depth = 256 ")
       (comment "c_has_default_data = 0 ")
       (comment "c_limit_data_pitch = 8 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_mem_init_file = rom256x16.mif ")
       (comment "c_default_data = 0 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_addr_width = 8 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell RAMB4_S16 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WE (direction INPUT))
                   (port EN (direction INPUT))
                   (port RST (direction INPUT))
                   (port CLK (direction INPUT))
                   (port (rename DI_0_ "DI<0>") (direction INPUT))
                   (port (rename DI_1_ "DI<1>") (direction INPUT))
                   (port (rename DI_2_ "DI<2>") (direction INPUT))
                   (port (rename DI_3_ "DI<3>") (direction INPUT))
                   (port (rename DI_4_ "DI<4>") (direction INPUT))
                   (port (rename DI_5_ "DI<5>") (direction INPUT))
                   (port (rename DI_6_ "DI<6>") (direction INPUT))
                   (port (rename DI_7_ "DI<7>") (direction INPUT))
                   (port (rename DI_8_ "DI<8>") (direction INPUT))
                   (port (rename DI_9_ "DI<9>") (direction INPUT))
                   (port (rename DI_10_ "DI<10>") (direction INPUT))
                   (port (rename DI_11_ "DI<11>") (direction INPUT))
                   (port (rename DI_12_ "DI<12>") (direction INPUT))
                   (port (rename DI_13_ "DI<13>") (direction INPUT))
                   (port (rename DI_14_ "DI<14>") (direction INPUT))
                   (port (rename DI_15_ "DI<15>") (direction INPUT))
                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))
                   (port (rename DO_1_ "DO<1>") (direction OUTPUT))
                   (port (rename DO_2_ "DO<2>") (direction OUTPUT))
                   (port (rename DO_3_ "DO<3>") (direction OUTPUT))
                   (port (rename DO_4_ "DO<4>") (direction OUTPUT))
                   (port (rename DO_5_ "DO<5>") (direction OUTPUT))
                   (port (rename DO_6_ "DO<6>") (direction OUTPUT))
                   (port (rename DO_7_ "DO<7>") (direction OUTPUT))
                   (port (rename DO_8_ "DO<8>") (direction OUTPUT))
                   (port (rename DO_9_ "DO<9>") (direction OUTPUT))
                   (port (rename DO_10_ "DO<10>") (direction OUTPUT))
                   (port (rename DO_11_ "DO<11>") (direction OUTPUT))
                   (port (rename DO_12_ "DO<12>") (direction OUTPUT))
                   (port (rename DO_13_ "DO<13>") (direction OUTPUT))
                   (port (rename DO_14_ "DO<14>") (direction OUTPUT))
                   (port (rename DO_15_ "DO<15>") (direction OUTPUT))
                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))
                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))
                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))
                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))
                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))
                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))
                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))
                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell rom256x16
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename addr "addr<7:0>") 8 ) (direction INPUT))
   (port ( rename clk "clk") (direction INPUT))
   (port ( rename en "en") (direction INPUT))
   (port ( array ( rename dout "dout<15:0>") 16 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance B5
      (viewRef view_1 (cellRef RAMB4_S16 (libraryRef xilinxun)))
      (property INIT_00 (string "0001800020001000080004000200010000800040002000100008000400020001"))
      (property INIT_01 (string "0002000180002000100008000400020001000080004000200010000800040002"))
      (property INIT_02 (string "0004000200018000200010000800040002000100008000400020001000080004"))
      (property INIT_03 (string "0008000400020001800020001000080004000200010000800040002000100008"))
      (property INIT_04 (string "0010000800040002000180002000100008000400020001000080004000200010"))
      (property INIT_05 (string "0020001000080004000200018000200010000800040002000100008000400020"))
      (property INIT_06 (string "0040002000100008000400020001800020001000080004000200010000800040"))
      (property INIT_07 (string "0080004000200010000800040002000180002000100008000400020001000080"))
      (property INIT_08 (string "0100008000400020001000080004000200018000200010000800040002000100"))
      (property INIT_09 (string "0200010000800040002000100008000400020001800020001000080004000200"))
      (property INIT_0A (string "0400020001000080004000200010000800040002000180002000100008000400"))
      (property INIT_0B (string "0800040002000100008000400020001000080004000200018000200010000800"))
      (property INIT_0C (string "1000080004000200010000800040002000100008000400020001800020001000"))
      (property INIT_0D (string "2000100008000400020001000080004000200010000800040002000180002000"))
      (property INIT_0E (string "8000200010000800040002000100008000400020001000080004000200018000"))
      (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef WE (instanceRef B5))
      (portRef RST (instanceRef B5))
      (portRef DI_0_ (instanceRef B5))
      (portRef DI_1_ (instanceRef B5))
      (portRef DI_2_ (instanceRef B5))
      (portRef DI_3_ (instanceRef B5))
      (portRef DI_4_ (instanceRef B5))
      (portRef DI_5_ (instanceRef B5))
      (portRef DI_6_ (instanceRef B5))
      (portRef DI_7_ (instanceRef B5))
      (portRef DI_8_ (instanceRef B5))
      (portRef DI_9_ (instanceRef B5))
      (portRef DI_10_ (instanceRef B5))
      (portRef DI_11_ (instanceRef B5))
      (portRef DI_12_ (instanceRef B5))
      (portRef DI_13_ (instanceRef B5))
      (portRef DI_14_ (instanceRef B5))
      (portRef DI_15_ (instanceRef B5))
    )
   )
   (net (rename N122 "addr<7>")
    (joined
      (portRef (member addr 0))
      (portRef ADDR_7_ (instanceRef B5))
    )
   )
   (net (rename N123 "addr<6>")
    (joined
      (portRef (member addr 1))
      (portRef ADDR_6_ (instanceRef B5))
    )
   )
   (net (rename N124 "addr<5>")
    (joined
      (portRef (member addr 2))
      (portRef ADDR_5_ (instanceRef B5))
    )
   )
   (net (rename N125 "addr<4>")
    (joined
      (portRef (member addr 3))
      (portRef ADDR_4_ (instanceRef B5))
    )
   )
   (net (rename N126 "addr<3>")
    (joined
      (portRef (member addr 4))
      (portRef ADDR_3_ (instanceRef B5))
    )
   )
   (net (rename N127 "addr<2>")
    (joined
      (portRef (member addr 5))
      (portRef ADDR_2_ (instanceRef B5))
    )
   )
   (net (rename N128 "addr<1>")
    (joined
      (portRef (member addr 6))
      (portRef ADDR_1_ (instanceRef B5))
    )
   )
   (net (rename N129 "addr<0>")
    (joined
      (portRef (member addr 7))
      (portRef ADDR_0_ (instanceRef B5))
    )
   )
   (net (rename N130 "clk")
    (joined
      (portRef clk)
      (portRef CLK (instanceRef B5))
    )
   )
   (net (rename N147 "dout<15>")
    (joined
      (portRef (member dout 0))
      (portRef DO_15_ (instanceRef B5))
    )
   )
   (net (rename N148 "dout<14>")
    (joined
      (portRef (member dout 1))
      (portRef DO_14_ (instanceRef B5))
    )
   )
   (net (rename N149 "dout<13>")
    (joined
      (portRef (member dout 2))
      (portRef DO_13_ (instanceRef B5))
    )
   )
   (net (rename N150 "dout<12>")
    (joined
      (portRef (member dout 3))
      (portRef DO_12_ (instanceRef B5))
    )
   )
   (net (rename N151 "dout<11>")
    (joined
      (portRef (member dout 4))
      (portRef DO_11_ (instanceRef B5))
    )
   )
   (net (rename N152 "dout<10>")
    (joined
      (portRef (member dout 5))
      (portRef DO_10_ (instanceRef B5))
    )
   )
   (net (rename N153 "dout<9>")
    (joined
      (portRef (member dout 6))
      (portRef DO_9_ (instanceRef B5))
    )
   )
   (net (rename N154 "dout<8>")
    (joined
      (portRef (member dout 7))
      (portRef DO_8_ (instanceRef B5))
    )
   )
   (net (rename N155 "dout<7>")
    (joined
      (portRef (member dout 8))
      (portRef DO_7_ (instanceRef B5))
    )
   )
   (net (rename N156 "dout<6>")
    (joined
      (portRef (member dout 9))
      (portRef DO_6_ (instanceRef B5))
    )
   )
   (net (rename N157 "dout<5>")
    (joined
      (portRef (member dout 10))
      (portRef DO_5_ (instanceRef B5))
    )
   )
   (net (rename N158 "dout<4>")
    (joined
      (portRef (member dout 11))
      (portRef DO_4_ (instanceRef B5))
    )
   )
   (net (rename N159 "dout<3>")
    (joined
      (portRef (member dout 12))
      (portRef DO_3_ (instanceRef B5))
    )
   )
   (net (rename N160 "dout<2>")
    (joined
      (portRef (member dout 13))
      (portRef DO_2_ (instanceRef B5))
    )
   )
   (net (rename N161 "dout<1>")
    (joined
      (portRef (member dout 14))
      (portRef DO_1_ (instanceRef B5))
    )
   )
   (net (rename N162 "dout<0>")
    (joined
      (portRef (member dout 15))
      (portRef DO_0_ (instanceRef B5))
    )
   )
   (net (rename N163 "en")
    (joined
      (portRef en)
      (portRef EN (instanceRef B5))
    )
   )
))))
(design rom256x16 (cellRef rom256x16 (libraryRef test_lib))
  (property X_CORE_INFO (string "blkmemsp_v5_0, Coregen 8.2.03i_ip3"))
  (property PART (string "xc2s15-cs144-6") (owner "Xilinx")))
)