count_top.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 89 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count_top is
    Port ( rst : in std_logic;
           clkin : in std_logic;
--		clkout: out std_logic;
           ce : in std_logic;
           ld : in std_logic;
           up : in std_logic;
           din : in std_logic_vector(15 downto 0);
           dout : out std_logic_vector(15 downto 0);
	     hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic);
end count_top;

architecture Behavioral of count_top is

component counter
	port(	CLK: in STD_LOGIC;
     		RESET: in STD_LOGIC;
     		CE, LOAD, DIR: in STD_LOGIC;
     		DIN: in STD_LOGIC_VECTOR(15 downto 0);
     		COUNT: inout STD_LOGIC_VECTOR(15 downto 0));
end component;

component HEX2LED_4 
    Port ( HEX : in std_logic_vector(15 downto 0);
           LED1 : out std_logic_vector(6 downto 0);
           LED2 : out std_logic_vector(6 downto 0);
           LED3 : out std_logic_vector(6 downto 0);
           LED4 : out std_logic_vector(6 downto 0));
end component;

component vga_16 
    Port ( clk : in std_logic;
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic;
	     innum  : in std_logic_vector(15 downto 0);
	     innum0 : in std_logic_vector(15 downto 0); 
           innum1 : in std_logic_vector(6 downto 0);
           innum2 : in std_logic_vector(6 downto 0);
           innum3 : in std_logic_vector(6 downto 0);
	     innum4 : in std_logic_vector(6 downto 0));
end component;
signal clk: std_logic;
signal N: std_logic_vector(23 downto 0);
signal do: std_logic_vector(15 downto 0);
signal HEX :  std_logic_vector(15 downto 0);
signal LED1 : std_logic_vector(6 downto 0);
signal LED2 : std_logic_vector(6 downto 0);
signal LED3 : std_logic_vector(6 downto 0);
signal LED4 : std_logic_vector(6 downto 0);

begin

process(clk, N)
begin
if (clkin'event and clkin='1') then
	N<=N+1;
end if;
end process;

clk<=N(23);

--clkout<=N(23);
U1: counter port map(clk,rst,ce,ld,up,din,do);

dout<=not do;

U2: HEX2LED_4 port map(do, led1,led2,led3,led4);

U3: vga_16 port map(clkin,hs,vs,r,g,b,do,do,led1,led2,led3,led4);

end Behavioral;