序列检测器.vhd

含有各类寄存器

library ieee;
use ieee.std_logic_1164.all;
entity stringe is
port (clk,choice,reset: in std_logic;
       qout,ps: out std_logic);
  constant s0:std_logic_vector(2 downto 0):="000";
  constant s1:std_logic_vector(2 downto 0):="001";
  constant s2:std_logic_vector(2 downto 0):="010";
  constant s3:std_logic_vector(2 downto 0):="011";
  constant s4:std_logic_vector(2 downto 0):="100";
  constant s5:std_logic_vector(2 downto 0):="101";
  constant s6:std_logic_vector(2 downto 0):="110";
  constant s7:std_logic_vector(2 downto 0):="111";

end ;

architecture aa of stringe is
COMPONENT trygen 
	PORT(
		clk,start,choice: IN	STD_LOGIC;
		pluse			: OUT	STD_LOGIC);
	END COMPONENT;

  signal state: std_logic_vector(2 downto 0);
  signal dout,din:std_logic;  
begin
trygenCOMPONENT: trygen 
	PORT MAP (
		clk=>clk,
		start=>reset,
		choice=>choice,
		pluse=>din);
ps<=din;
process (clk,reset)
begin
if reset='0' then state<="000";
 elsif(clk'event and clk='1')then
  case state  is
    when "000" =>
      if din='1' then 
          state<=s1;
          dout<='0';
       else
          state<=s0;
          dout<='0';
       end if;
    when "001" =>
      if din='1' then 
          state<=s2;
          dout<='0';
       else
          state<=s0;
          dout<='0';
       end if;
    when "010" =>
      if din='1' then 
          state<=s3;
          dout<='0';
       else
          state<=s0;
          dout<='0';
       end if;
    when "011" =>
      if din='1' then 
          state<=s3;
          dout<='0';
       else
          state<=s4;
          dout<='0';
       end if;
    when "100" =>
      if din='1' then 
          state<=s1;
          dout<='0';
       else
          state<=s5;
          dout<='0';
       end if;
    when "101" =>
      if din='1' then 
          state<=s6;
          dout<='0';
       else
          state<=s0;
          dout<='0';
       end if;
    when "110" =>
      if din='1' then 
          state<=s2;
          dout<='0';
       else
          state<=s7;
          dout<='1';
       end if;
    when "111" =>
      if din='1' then 
          state<=s1;
          dout<='0';
       else
          state<=s0;
          dout<='0';
       end if;
    when others =>
         state<=s0;
         dout<='0';
    end case;
 end if;

 qout<=dout; 
end process;
end aa;
 

library ieee;
use ieee.std_logic_1164.all;
ENTITY trygen IS
	PORT(
		clk,start,choice: IN	STD_LOGIC;
		pluse			: OUT	STD_LOGIC);
END trygen;
ARCHITECTURE aa OF trygen IS
	SIGNAL count : STD_LOGIC_vector(2 downto 0);
BEGIN
gen_label:
PROCESS (clk,start)
BEGIN
IF clk'event and clk='1' THEN
IF start='0'  THEN
    count<="000";
ELSE
    IF choice='1' THEN 
    CASE count IS
    	WHEN "000" =>
    	    count<="001";
    	    pluse<='1';
    	WHEN "001" =>
    	    count<="010";
    	    pluse<='1';
    	WHEN "010" =>
    	    count<="011";
    	    pluse<='1';
    	WHEN "011" =>
    	    count<="100";
    	    pluse<='0';
    	WHEN "100" =>
    	    count<="101";
    	    pluse<='0';
    	WHEN "101" =>
    	    count<="110";
    	    pluse<='1';
    	WHEN "110" =>
    	    count<="111";
    	    pluse<='0';
    	WHEN OTHERS =>
    	    count<="000";
    	    pluse<='0';
    END CASE;
    ELSE
    CASE count IS
    	WHEN "000" =>
    	    count<="001";
    	    pluse<='1';
    	WHEN "001" =>
    	    count<="010";
    	    pluse<='0';
    	WHEN "010" =>
    	    count<="011";
    	    pluse<='1';
    	WHEN "011" =>
    	    count<="100";
    	    pluse<='0';
    	WHEN "100" =>
    	    count<="101";
    	    pluse<='1';
    	WHEN "101" =>
    	    count<="110";
    	    pluse<='0';
    	WHEN "110" =>
    	    count<="111";
    	    pluse<='1';
    	WHEN OTHERS =>
    	    count<="000";
    	    pluse<='0';
    END CASE;
END IF;
END IF;
END IF;

END PROCESS gen_label;

END aa;