16bit模数转换器.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 30 行

--16-bit Analogue to Digital Converter
USE WORK.rampac.ALL;
USE WORK.adcpac.ALL;
ENTITY adc16 IS
GENERIC(tconv : TIME := 10 us); --conversion time
PORT(vin : IN analogue; digout : OUT data16; --input and output
sc : IN BIT; busy : OUT BIT); --control
END adc16;
ARCHITECTURE behaviour OF adc16 IS
BEGIN
  PROCESS
  VARIABLE digtemp : data16;
  CONSTANT vlsb : analogue := (analogue'HIGH -
                               analogue'LOW)/REAL(2*ABS(data16'LOW));
BEGIN
     digtemp := data16'LOW;
        busy <= '0';
WAIT UNTIL (sc'EVENT AND sc = '0');
       busy <= '1';
FOR i IN 0 TO (2*data16'HIGH) LOOP
    IF vin >= (analogue'LOW + (REAL(i) + 0.5)*vlsb)
    THEN digtemp := digtemp + 1;
    ELSE EXIT;
    END IF;
END LOOP;
   WAIT FOR tconv;
        digout <= digtemp;
          busy <= '0';
   END PROCESS;
END behaviour;