shift_8bit.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 43 行

--Structural Description of an 8-bit Shift Register
ENTITY dtff IS
    GENERIC(initial : BIT := '1'); --initial value of q
      PORT(d, clock : IN BIT; q : BUFFER BIT := initial);
END dtff;
ARCHITECTURE zero_delay OF dtff IS
BEGIN
    q <= d WHEN (clock'EVENT AND clock = '1');
END zero_delay;
--Structural model of an 8-bit universal shift register
--makes use of D-type flip flop component and generate statement
ENTITY shftreg8 IS
     PORT(clock, serinl, serinr : IN BIT; mode : IN BIT_VECTOR(0 TO 1);
                          parin : IN BIT_VECTOR(0 TO 7);
                         parout : BUFFER BIT_VECTOR(0 TO 7));
END shftreg8;
ARCHITECTURE structural OF shftreg8 IS
COMPONENT dtff
GENERIC(initial : BIT := '1');
         PORT(d, clock : IN BIT; q : BUFFER BIT := initial);
END COMPONENT;
     FOR ALL : dtff USE ENTITY work.dtff(zero_delay);
SIGNAL datain : BIT_VECTOR(0 TO 7);
BEGIN
         reg_cells : FOR i IN 0 TO 7
GENERATE
         reg_stage : dtff GENERIC MAP ('0') PORT MAP (datain(i) , clock, parout(i));
         lsb_stage : IF i = 0 GENERATE
         datain(i) <= parin(i) WHEN mode = "00" ELSE serinl WHEN mode = "10"
ELSE parout(i + 1) WHEN mode = "01" ELSE parout(i);
END GENERATE;
msb_stage : IF i = 7 GENERATE
datain(i) <= parin(i) WHEN mode = "00" ELSE parout(i - 1) WHEN mode =
"10"
ELSE serinr WHEN mode = "01" ELSE parout(i);
END GENERATE;
    middle_stages : IF (i > 0) AND (i < 7) GENERATE
datain(i) <= parin(i) WHEN mode = "00" ELSE parout(i - 1) WHEN mode =
"10"
     ELSE parout(i + 1) WHEN mode = "01" ELSE parout(i);
     END GENERATE;
     END GENERATE;
END structural;