r74194.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 29 行

library IEEE;
use IEEE.std_logic_1164.all;
entity R74194 is
    port (    CP: in STD_LOGIC;
        RD: in STD_LOGIC;
        S: in STD_LOGIC_VECTOR (1 downto 0);
        D: in STD_LOGIC_VECTOR (3 downto 0);
        DSL: in STD_LOGIC;
        DSR: in STD_LOGIC;
        Q: inout STD_LOGIC_VECTOR (3 downto 0) );
end R74194;
architecture R74194_arch of R74194 is
begin
   process (CP,RD,S) 
variable F: STD_LOGIC_VECTOR (3 downto 0);
 begin
           if  RD='0' then Q<="0000";F:="0000";
           elsif  CP='0' and CP'event then 
           if  S(0)='1' and S(1)='1' then F:=D;
           elsif S(0)='1' and S(1)='0' then F(0):=DSR;F(1):=Q(0);F(2):=Q(1);F(3):=Q(2);
           elsif S(0)='0' and S(1)='1' then F(3):=DSL;F(2):=Q(3);F(1):=Q(2);F(0):=Q(1);
           elsif S(0)='0' and S(1)='0' then F:=Q;
           end if;
           Q<=F; 
           end if;   
           end process;
          
 end R74194_arch;