74138.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 29 行

entity DEC_138 is
       port( I : in bit_vector(2 downto 0);                     -- data input
                G1, G2A_N, G2B_N    : in bit;               -- enable signals
                Y_N    : out bit_vector(7 downto 0));          --  output lines
end DEC_138;
architecture DEC3_8 of DEC_138 is
signal EN:    bit;                                 -- local enable
begin
 EN <= (G1 and not G2A_N and not G2B_N);
process (I, EN)
variable TEMP: bit_vector(3 downto 0);          -- local test variable
       begin
       Y_N <= (others => '1');                  -- default assignment; aggregate
       TEMP := EN & I   ;                    -- concatenation: vector & bit
           case TEMP is
              when "1000"     => Y_N(0)  <=  '0';
              when "1001"     => Y_N(1)  <=  '0';
              when "1010"     => Y_N(2)  <=  '0';
              when "1011"     => Y_N(3)  <=  '0';
              when "1100"     => Y_N(4)  <=  '0';
              when "1101"     => Y_N(5)  <=  '0';
              when "1110"     => Y_N(6)  <=  '0';
              when "1111"     => Y_N(7)  <=  '0';
              when others      =>  null;                  -- no assignment
           end case;
           end process;    
           end DEC3_8;