mod_16counter.vhd

含有各类寄存器

--Mod-16 Counter using JK Flip-flops
--Structural description of a 4-bit binary counter. The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. These are then packaged together along with a signal named 'tied_high' into a package named
--'jkpack'. The counter design uses the package 'jkpack', giving it access to the components and the signal declared within the package. The flip-flops and AND-gates are wired together to form a counter. Notice the use of the keyword
--OPEN to indicate an open-cct output port.
ENTITY jkff IS
PORT(clock, j, k : IN BIT; q, qbar : BUFFER BIT);
END jkff;
ARCHITECTURE using_process OF jkff IS
BEGIN
--sequential process to model JK flip-flop
PROCESS
--declare a local variable to hold ff state
VARIABLE state : BIT := '0';
BEGIN
--synchronise process to rising edge of clock
WAIT UNTIL (clock'EVENT AND clock = '1');
IF (j = '1' AND k = '1') THEN --toggle
state := NOT state;
ELSIF (j = '0' AND k = '1') THEN --reset
state := '0';
ELSIF (j = '1' AND k = '0') THEN --set
state := '1';
ELSE --no change
state := state;
END IF;
--assign values to output signals
q <= state AFTER 5 ns;
qbar <= NOT state AFTER 5 ns;
END PROCESS;
END using_process;


ENTITY and_gate IS
PORT(a, b : IN BIT; f : OUT BIT);
END and_gate;
ARCHITECTURE simple OF and_gate IS
BEGIN
f <= a AND b AFTER 2 ns;
END simple;
PACKAGE jkpack IS
SIGNAL tied_high : BIT := '1';
COMPONENT jkff
PORT(clock, j, k : IN BIT; q, qbar : BUFFER BIT);
END COMPONENT;
COMPONENT and_gate
PORT(a, b : IN BIT; f : OUT BIT);
END COMPONENT;
END jkpack;
USE work.jkpack.ALL;
ENTITY mod16_cntr IS
PORT(clock : IN BIT; count : BUFFER BIT_VECTOR(0 TO 3));
END mod16_cntr;
ARCHITECTURE net_list OF mod16_cntr IS
SIGNAL s1,s2 : BIT;
BEGIN
a1 : and_gate PORT MAP (count(0),count(1),s1);
a2 : and_gate PORT MAP (s1, count(2), s2);
jk1 : jkff PORT MAP (clock,tied_high,tied_high,count(0),OPEN);
jk2 : jkff PORT MAP (clock,count(0),count(0),count(1),OPEN);
jk3 : jkff PORT MAP (clock,s1,s1,count(2),OPEN);
jk4 : jkff PORT MAP (clock,s2,s2,count(3),OPEN);
END net_list;