counter_using_multiple_wait.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 26 行

--Counter using Multiple Wait Statements
--This example shows an inefficient way of describing a counter.
--vhdl model of a 3-state counter illustrating the use
--of the WAIT statement to suspend a process.At each wait
--statement the simulation time is updated one cycle,transferring
--the driver value to the output count.
--This architecture shows that there is no difference between
--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'
ENTITY cntr3 IS
PORT(clock : IN BIT; count : OUT NATURAL);
END cntr3;
ARCHITECTURE using_wait OF cntr3 IS
BEGIN
PROCESS
BEGIN
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 0;
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 1;
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 2;
END PROCESS;
END using_wait;