nbit_synchronous_counter.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 25 行

--n-Bit Synchronous Counter
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(n : Positive := 8);
PORT(clock, reset, enable : IN Std_logic;
count : OUT Std_logic_vector((n-1) DOWNTO 0));
END cntrnbit;
ARCHITECTURE v1 OF cntrnbit IS
SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF reset = '1' THEN
count_int <= (OTHERS => '0');
ELSIF enable = '1' THEN
count_int <= count_int + 1;
ELSE
NULL;
END IF;
END PROCESS;
count <= count_int;
END v1;