radarsima.vhd

含有各类寄存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RadarSimA is
    Port ( TRIG_OUT				:	out	std_logic;
           TRIG_KEY_IN			:	in		std_logic;
           AZIP_OUT				:	out	std_logic;
           AZIP_KEY_IN			:	in		std_logic;
           SHF_OUT				:	out	std_logic;
			  VIDEO_OUT				:	out	std_logic;

           RST_IN					:	in		std_logic;
           CLK_IN					:	in		std_logic;
           AZIP_LED_COMMON		:	buffer std_logic_vector(3 downto 0);		--方位显示数码管公共端
           TRIG_LED_COMMON		:	buffer std_logic_vector(3 downto 0);		--触发显示数码管公共端
           TRIG_LED				:	out	std_logic_vector(6 downto 0);
           AZIP_LED				:	out	std_logic_vector(6 downto 0);
			  trigkey_test			:	out	std_logic
--			  temp					:	out	std_logic;
			  );
end RadarSimA;

architecture Behavioral of RadarSimA is

	component TargetGen
	    Port (
				FIX_OUT_3V		:	out	std_logic;
				FIX_OUT_0V5		:	out	std_logic;
				MOV_OUT_1		:	out	std_logic;
				MOV_OUT_3		:	out	std_logic;
				RING_5NM			:	out	std_logic;
	 			CLK_IN			:	in		std_logic;
				RST_IN			:	in		std_logic;
				TRIG_OUT			:	out	std_logic;
				HEAD_OUT			:	out	std_logic;
				AZIP_OUT			:	out	std_logic;
				TRIG_SEL			:	in		std_logic_vector(2 downto 0);
				AZIP_SEL			:	in		std_logic_vector(1 downto 0)
				 );
	end component;

	component UserInterface
	 Port ( CLK_IN				:	in std_logic;										--外部时钟输入，使用38.83951MHz晶振
			  RST_IN				:	in std_logic;										--RESET按键输入
	 		  TRIG_KEY_IN		:	in std_logic;										--触发选择按键输入
           AZIP_KEY_IN		:	in std_logic;										--方位选择按键输入
           TRIG_LED			:	out std_logic_vector(6 downto 0);			--触发频率显示数码管输出
           AZIP_LED			:	out std_logic_vector(6 downto 0);			--方位脉冲数显示数码管输出
           AZIP_LED_COMMON		:	buffer std_logic_vector(3 downto 0);		--方位显示数码管公共端
           TRIG_LED_COMMON		:	buffer std_logic_vector(3 downto 0);		--触发显示数码管公共端
           TRIG_SEL_OUT		:	buffer std_logic_vector(2 downto 0);		--触发频率选择输出，到目标产生模块
           AZIP_SEL_OUT		:	buffer std_logic_vector(1 downto 0);			--方位脉冲数选择输出，到目标产生模块
			  trigkeytest		:	out std_logic
			  );	
	end component;

	signal	MovOut1			:		std_logic;
	signal	MovOut3			:		std_logic;
	signal	FixOut3V			:		std_logic;
	signal	FixOut0V5		:		std_logic;
	signal	ShfOut			:		std_logic;
	signal	Ring5Nm			:		std_logic;
	signal	TrigSel			:		std_logic_vector(2 downto 0);
	signal	AzipSel			:		std_logic_vector(1 downto 0);
	signal	aa					:		std_logic;

begin

	INST_TARGETGEN	:	TargetGen port map(
		FIX_OUT_3V		=> FixOut3V,
		FIX_OUT_0V5		=> FixOut0V5,
		MOV_OUT_1		=> MovOut1,
		MOV_OUT_3		=> MovOut3,
		RING_5NM			=>	Ring5Nm,
		CLK_IN			=> CLK_IN,
		RST_IN			=> RST_IN,
		TRIG_OUT			=> TRIG_OUT,
		HEAD_OUT			=> ShfOut,
		AZIP_OUT			=> AZIP_OUT,
		TRIG_SEL			=> TrigSel,
		AZIP_SEL			=> AzipSel
	);

	INST_USERINTERFACE	:	UserInterface port map(
		CLK_IN			=> aa,
		RST_IN			=> RST_IN,
		TRIG_KEY_IN		=> TRIG_KEY_IN,
		AZIP_KEY_IN		=> AZIP_KEY_IN,
		TRIG_LED			=> TRIG_LED,
		AZIP_LED			=> AZIP_LED,
		AZIP_LED_COMMON		=> AZIP_LED_COMMON,
		TRIG_LED_COMMON		=>	TRIG_LED_COMMON,
		TRIG_SEL_OUT	=> TrigSel,
		AZIP_SEL_OUT	=> AzipSel,
		trigkeytest		=> trigkey_test
	);

	VIDEO_OUT	<=	FixOut3V or FixOut0V5 or MovOut1 or MovOut3 or Ring5Nm;
	aa				<=	CLK_IN;

	SHF_OUT		<=	 not ShfOut;

end Behavioral;