📄 targetgen.vhd
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-------------------------------------------------------------------------------
-- 文件名: TargetGen.vhd
-- Copyright (c) 2002-2003 SVA-Radar信息产品部
-- 创建人: 马骏
-- 日 期: 5/12/2002
-- 修改人: 马骏
-- 日 期: 2/28/2003
-- 描 述: 雷达模拟器v1.0目标产生模块
-- 版 本: 1.0
-------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PackForSim.all;
entity TargetGen is
Port (
----------------------------------------------------------
--仿真信号输出
-- TRIG_OUT_1K8 : out std_logic;
-- TRIG_OUT_1K2 : out std_logic;
-- TRIG_OUT_0K6 : out std_logic;
-- TRIG_OUT_1K3 : out std_logic;
-- TRIG_OUT_0K65 : out std_logic;
-- AZIP_OUT_216 : out std_logic;
-- AZIP_OUT_360 : out std_logic;
-- AZIP_OUT_1080 : out std_logic;
FIX_OUT_3V : out std_logic;
FIX_OUT_0V5 : out std_logic;
MOV_OUT_1 : out std_logic;
MOV_OUT_3 : out std_logic;
RING_5NM : out std_logic;
----------------------------------------------------------
CLK_IN : in std_logic;
RST_IN : in std_logic;
TRIG_OUT : out std_logic;
HEAD_OUT : out std_logic;
AZIP_OUT : out std_logic;
TRIG_SEL : in std_logic_vector(2 downto 0);
AZIP_SEL : in std_logic_vector(1 downto 0)
);
end TargetGen;
architecture Behavioral of TargetGen is
signal ClkTrig : std_logic;
signal ClkAzip : std_logic;
signal ClkShf : std_logic;
signal ClkTrgt : std_logic;
signal Rst : std_logic;
signal TrigOut : std_logic;
signal TrigOut_1k8 : std_logic;
signal TrigOut_1k2 : std_logic;
signal TrigOut_0k6 : std_logic;
signal TrigOut_1k3 : std_logic;
signal TrigOut_0k65 : std_logic;
signal AzipOut : std_logic;
signal AzipOut_90 : std_logic;
signal AzipOut_216 : std_logic;
signal AzipOut_360 : std_logic;
signal AzipOut_1080 : std_logic;
signal ShfOut : std_logic;
signal FixTrgt05vAzipEn : boolean; --0.5v固定目标方位使能信号
signal FixTrgt05vVideoOut : std_logic;
signal FixTrgt3vAzipEn : boolean;
signal FixTrgt3vVideoOut : std_logic;
signal TrigPeriod : integer range 0 to 16#FFFF#; --不同的触发脉冲周期中包含的原始时钟数，最大为FCDD个
signal FixTrgt05vHalfWidth : integer range 0 to MaxTrgtBeamNum*16#FFFF#; --0.5v固定目标宽度计数的一半
signal FixTrgt3vHalfWidth : integer range 0 to MaxTrgtBeamNum*16#FFFF#; --3v固定目标宽度计数的一半
signal MovTrgtHalfWidth : integer range 0 to MaxTrgtBeamNum*16#FFFF#;
signal MovTrgt1AzipEn : boolean;
signal MovTrgt2AzipEn : boolean;
signal MovTrgt3AzipEn : boolean;
signal MovTrgt1VideoOut : std_logic;
-- signal MovTrgt2VideoOut : std_logic;
signal MovTrgt3VideoOut : std_logic;
signal Ring5Nm : std_logic;
signal MovTrgt1RngCnt : integer range 0 to RadarRng;
signal MovTrgt3RngCnt : integer range 0 to RadarRng;
begin
------------------------------------------------------------------------
--触发信号产生模块
TRIGGER_1K8_GENERATE:
process(ClkTrig, Rst)
variable cnt : integer range 0 to Trig1k8Cnt;
begin
if(Rst = '1') then
TrigOut_1k8 <= '0';
cnt := 0;
elsif rising_edge(ClkTrig) then
if(cnt = Trig1k8Cnt) then
cnt := 0;
end if;
if(cnt < TrigWidthCnt) then
TrigOut_1k8 <= '1';
else
TrigOut_1k8 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
TRIGGER_1K2_GENERATE:
process(ClkTrig, Rst)
variable cnt : integer range 0 to Trig1k2Cnt;
begin
if(Rst = '1') then
TrigOut_1k2 <= '0';
cnt := 0;
elsif rising_edge(ClkTrig) then
if(cnt = Trig1k2Cnt) then
cnt := 0;
end if;
if(cnt < TrigWidthCnt) then
TrigOut_1k2 <= '1';
else
TrigOut_1k2 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
TRIGGER_0K6_GENERATE:
process(ClkTrig, Rst)
variable cnt : integer range 0 to Trig0k6Cnt;
begin
if(Rst = '1') then
TrigOut_0k6 <= '0';
cnt := 0;
elsif rising_edge(ClkTrig) then
if(cnt = Trig0k6Cnt) then
cnt := 0;
end if;
if(cnt < TrigWidthCnt) then
TrigOut_0k6 <= '1';
else
TrigOut_0k6 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
TRIGGER_1K3_GENERATE:
process(ClkTrig, Rst)
variable cnt : integer range 0 to Trig1k3Cnt;
begin
if(Rst = '1') then
TrigOut_1k3 <= '0';
cnt := 0;
elsif rising_edge(ClkTrig) then
if(cnt = Trig1k3Cnt) then
cnt := 0;
end if;
if(cnt < TrigWidthCnt) then
TrigOut_1k3 <= '1';
else
TrigOut_1k3 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
TRIGGER_0K65_GENERATE:
process(ClkTrig, Rst)
variable cnt : integer range 0 to Trig0k65Cnt;
begin
if(Rst = '1') then
TrigOut_0k65 <= '0';
cnt := 0;
elsif rising_edge(ClkTrig) then
if(cnt = Trig0k65Cnt) then
cnt := 0;
end if;
if(cnt < TrigWidthCnt) then
TrigOut_0k65 <= '1';
else
TrigOut_0k65 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
-- sel code freqency out
-- 000 1300Hz
-- 001 650Hz
-- 010 1800Hz
-- 011 1200Hz
-- 100 600Hz
-- other Z
TRIGGER_SELECTE:
process(TRIG_SEL, TrigOut_1k3, TrigOut_0k65,
TrigOut_1k8, TrigOut_1k2, TrigOut_0k6)
begin
if (TRIG_SEL = "000") then
TrigOut <= TrigOut_1k3;
TrigPeriod <= TrigPeriod1k3;
elsif (TRIG_SEL = "001") then
TrigOut <= TrigOut_0k65;
TrigPeriod <= TrigPeriod0k65;
elsif (TRIG_SEL = "010") then
TrigOut <= TrigOut_1k8;
TrigPeriod <= TrigPeriod1k8;
elsif (TRIG_SEL = "011") then
TrigOut <= TrigOut_1k2;
TrigPeriod <= TrigPeriod1k2;
elsif (TRIG_SEL = "100") then
TrigOut <= TrigOut_0k6;
TrigPeriod <= TrigPeriod0k6;
else
TrigOut <= 'Z';
TrigPeriod <= 0;
end if;
end process;
------------------------------------------------------------------------
------------------------------------------------------------------------
--方位信号产生模块
AZIP_90_GENERATE:
process(ClkAzip, Rst)
variable cnt : integer range 0 to Azip90Cnt;
begin
if(Rst = '1') then
cnt := 0;
AzipOut_90 <= '0';
elsif rising_edge(ClkAzip) then
if(cnt = Azip90Cnt) then
cnt := 0;
end if;
if(cnt < AzipWidthCnt) then
AzipOut_90 <= '1';
else
AzipOut_90 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
AZIP_216_GENERATE:
process(ClkAzip, Rst)
variable cnt : integer range 0 to Azip216Cnt;
begin
if(Rst = '1') then
cnt := 0;
AzipOut_216 <= '0';
elsif rising_edge(ClkAzip) then
if(cnt = Azip216Cnt) then
cnt := 0;
end if;
if(cnt < AzipWidthCnt) then
AzipOut_216 <= '1';
else
AzipOut_216 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
AZIP_360_GENERATE:
process(ClkAzip, Rst)
variable cnt : integer range 0 to Azip360Cnt;
begin
if(Rst = '1') then
cnt := 0;
AzipOut_360 <= '0';
elsif rising_edge(ClkAzip) then
if(cnt = Azip360Cnt) then
cnt := 0;
end if;
if(cnt < AzipWidthCnt) then
AzipOut_360 <= '1';
else
AzipOut_360 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
AZIP_1080_GENERATE:
process(ClkAzip, Rst)
variable cnt : integer range 0 to Azip1080Cnt;
begin
if(Rst = '1') then
cnt := 0;
AzipOut_1080 <= '0';
elsif rising_edge(ClkAzip) then
if(cnt = Azip1080Cnt) then
cnt := 0;
end if;
if(cnt < AzipWidthCnt) then
AzipOut_1080 <= '1';
else
AzipOut_1080 <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
-- sel code pulse per round
-- 00 216
-- 01 360
-- 10 1080
-- 11 90
AZIP_SELECT:
AzipOut <= AzipOut_216 when AZIP_SEL = "00" else
AzipOut_360 when AZIP_SEL = "01" else
AzipOut_1080 when AZIP_SEL = "10" else
AzipOut_90 when AZIP_SEL = "11" else
'Z';
------------------------------------------------------------------------
------------------------------------------------------------------------
--船首信号产生模块
SHIP_HEAD_FLAG_GENERATE:
process(ClkShf, Rst)
variable cnt : integer range 0 to ShfCnt;
begin
if(Rst = '1') then
cnt := 0;
ShfOut <= '0';
elsif rising_edge(ClkShf) then
if(cnt = ShfCnt) then
cnt := 0;
end if;
if(cnt < 38839) then
ShfOut <= '1';
else
ShfOut <= '0';
end if;
cnt := cnt + 1;
end if;
end process;
------------------------------------------------------------------------
------------------------------------------------------------------------
--产生0.5v固定目标
FIX_TARGET_05V_AZIP_ENABLE_GENERATE:
process(ClkTrgt, Rst, ShfOut, FixTrgt05vHalfWidth)
--一个天线扫掠周期为5C99C17（38.83951MHzx2.5）个脉冲，cnt范围大于一个天线扫掠周期即可
variable cnt : integer range 0 to 16#5FFFFFF#;
variable shfout_r : std_logic;
begin
if(Rst = '1') then
cnt := 0;
shfout_r := '0';
FixTrgt05vAzipEn <= false;
elsif rising_edge(ClkTrgt) then
if(ShfOut = '1' and shfout_r = '0') then
cnt := 0;
FixTrgt05vAzipEn <= false;
end if;
--目标的中心方位在FixTrgt3Azip上
if(cnt >= FixTrgt3Azip - FixTrgt05vHalfWidth
and cnt <= FixTrgt3Azip + FixTrgt05vHalfWidth) then
FixTrgt05vAzipEn <= true;
--目标的中心方位在FixTrgt4Azip上
elsif(cnt >= FixTrgt4Azip - FixTrgt05vHalfWidth
and cnt <= FixTrgt4Azip + FixTrgt05vHalfWidth) then
FixTrgt05vAzipEn <= true;
else
FixTrgt05vAzipEn <= false;
end if;
cnt := cnt + 1;
shfout_r := ShfOut;
end if;
end process;
FixTrgt05vHalfWidth <= FixTrgtBeamHalfNum * TrigPeriod;
FIX_TARGET_05V_GENERATE:
process(ClkTrgt, Rst, FixTrgt05vAzipEn, TrigOut)
--5种触发频率中，两脉冲间包括晶振周期最多的是FCDD个（600Hz的触发脉冲），
--目标距离计数的上限只要大于这个值即可，取FFFF
variable cnt : integer range 0 to 16#FFFF#;
variable trigout_r : std_logic;
begin
if(Rst = '1') then
cnt := 0;
trigout_r := '0';
FixTrgt05vVideoOut <= '0';
elsif rising_edge(ClkTrgt) then
if(FixTrgt05vAzipEn) then
if(TrigOut = '1' and trigout_r = '0') then
cnt := 0;
end if;
if(cnt >= FixTrgt05vRng - FixTrgt05vHalfLength
and cnt <= FixTrgt05vRng + FixTrgt05vHalfLength) then
FixTrgt05vVideoOut <= '1';
else
FixTrgt05vVideoOut <= '0';
end if;
cnt := cnt + 1;
trigout_r := TrigOut;
else
FixTrgt05vVideoOut <= '0';
cnt := 0;
end if;
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