fft_2s.v

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file fft_2s.v when simulating
// the core, fft_2s. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module fft_2s(
	clk,
	ce,
	reset,
	start,
	fwd_inv,
	mrd,
	mwr,
	xn_re,
	xn_im,
	ovflo,
	done,
	edone,
	busy,
	xk_re,
	xk_im);


input clk;
input ce;
input reset;
input start;
input fwd_inv;
input mrd;
input mwr;
input [7 : 0] xn_re;
input [7 : 0] xn_im;
output ovflo;
output done;
output edone;
output busy;
output [7 : 0] xk_re;
output [7 : 0] xk_im;

// synopsys translate_off

      VFFT32_V3_0 #(
		8,	// butterfly_precision
		0,	// c_family_int
		"block_mem",	// data_memory
		3,	// memory_architecture
		0,	// mult_type
		8,	// phase_factor_precision
		"fft_2s_mem1.mif",	// scaling_schedule_mem1
		"fft_2s_mem2.mif")	// scaling_schedule_mem2
	inst (
		.CLK(clk),
		.CE(ce),
		.RESET(reset),
		.START(start),
		.FWD_INV(fwd_inv),
		.MRD(mrd),
		.MWR(mwr),
		.XN_RE(xn_re),
		.XN_IM(xn_im),
		.OVFLO(ovflo),
		.DONE(done),
		.EDONE(edone),
		.BUSY(busy),
		.XK_RE(xk_re),
		.XK_IM(xk_im),
		.IO(),
		.EIO());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of fft_2s is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fft_2s is "black_box"

endmodule