test_ram.vhd

来自「含有各类寄存器」· VHDL 代码 · 共 26 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_RAM is
    Port ( CLK : in std_logic;
           RST : in std_logic;
           ADDR : in std_logic_vector(7 downto 0);
           DIN : in std_logic;
           WE : in std_logic;
           DOUT : out std_logic_vector(15 downto 0));
end test_RAM;

architecture Behavioral of test_RAM is

begin


end Behavioral;