count_top.vhd

含有各类寄存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count_top is
    Port ( CLKIN : in std_logic;
           RST : in std_logic;
           CE : in std_logic;
		 start: IN std_logic;
--		 fwd_inv: IN std_logic;
		 mrd: IN std_logic;
		 mwr: IN std_logic;
		 xn_re: IN std_logic_VECTOR(7 downto 0);
		 xn_im: IN std_logic_VECTOR(7 downto 0);
		 ovflo: OUT std_logic;
		 done: OUT std_logic;
		 edone: OUT std_logic;
		 busy: OUT std_logic;
		 xk_re: OUT std_logic_VECTOR(7 downto 0);
		 xk_im: OUT std_logic_VECTOR(7 downto 0);
           LD : in std_logic;
           UP : in std_logic;
           DIN : in std_logic_vector(7 downto 0);
		 LEDG: out std_logic;
           DOUT : out std_logic_vector(7 downto 0));
end count_top;

architecture Behavioral of count_top is

component CLKDLL
      port (CLKIN, CLKFB, RST : in STD_LOGIC;
      CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
 
component IBUFG
      port (I : in STD_LOGIC; O : out std_logic);
end component;
 
component BUFG
      port (I : in STD_LOGIC; O : out std_logic);
end component;

component SRL16
--
  generic (
       INIT : bit_vector := X"0000");
--
  port (D   : in STD_logic;
        CLK : in STD_logic;
        A0  : in STD_logic;
        A1  : in STD_logic;
        A2  : in STD_logic;
        A3  : in STD_logic;
        Q   : out STD_logic); 
end component;

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component counter
	port (
	Q: OUT std_logic_VECTOR(7 downto 0);
	CLK: IN std_logic;
	UP: IN std_logic;
	LOAD: IN std_logic;
	L: IN std_logic_VECTOR(7 downto 0);
	CE: IN std_logic;
	ACLR: IN std_logic);
end component;

-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of counter: component is "true";

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of counter: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component fft_2s
	port (
	clk: IN std_logic;
	ce: IN std_logic;
	reset: IN std_logic;
	start: IN std_logic;
	fwd_inv: IN std_logic;
	mrd: IN std_logic;
	mwr: IN std_logic;
	xn_re: IN std_logic_VECTOR(7 downto 0);
	xn_im: IN std_logic_VECTOR(7 downto 0);
	ovflo: OUT std_logic;
	done: OUT std_logic;
	edone: OUT std_logic;
	busy: OUT std_logic;
	xk_re: OUT std_logic_VECTOR(7 downto 0);
	xk_im: OUT std_logic_VECTOR(7 downto 0));
end component;

-- FPGA Express Black Box declaration
--attribute fpga_dont_touch: string;
attribute fpga_dont_touch of fft_2s: component is "true";

-- Synplicity black box declaration
--attribute syn_black_box : boolean;
attribute syn_black_box of fft_2s: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

signal CLK,CLK_IN,CLK2X,CLK_2X,LOCKED,CLK4X,LOCKED2: std_logic;
signal N: std_logic_vector(23 downto 0);
signal fwd_inv,logic0,logic1,RESET:  std_logic;
begin
LEDG<='1';
fwd_inv<='1';
logic0<=not RST;
logic1<='1';
U1: IBUFG port map (I=>CLKIN, O=>CLK_IN);
 
U2: CLKDLL port map (CLKIN=>CLK_IN, CLKFB=>CLK2X, RST=>logic0, 
                         CLK2X=>CLK_2X, LOCKED=>LOCKED);
 
U3: BUFG port map (I=>CLK4X, O=>CLK);

U4: BUFG port map (I=>CLK_2X, O=>CLK2X);

U5: CLKDLL port map (CLKIN=>CLK2X, CLKFB=>CLK, RST=>logic0,CLK2X=>CLK4X, LOCKED=>LOCKED2);

--U9: SRL16 port map (LOCKED,CLK2X,logic1,logic1,logic1,logic1,reset);
process(clk)
begin
if clk'event and clk='1' then
	N<=N+1;
end if;
end process;
--clk_in<=N(23);
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
U6 : counter
		port map (
			Q => dout,
			CLK => CLK,
			UP => UP,
			LOAD => LD,
			L => Din,
			CE => CE,
			ACLR => rst);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
U7 : fft_2s
		port map (
			clk => clk,
			ce => CE,
			reset => RST,
			start => start,
			fwd_inv => fwd_inv,
			mrd => mrd,
			mwr => mwr,
			xn_re => xn_re,
			xn_im => xn_im,
			ovflo => ovflo,
			done => done,
			edone => edone,
			busy => busy,
			xk_re => xk_re,
			xk_im => xk_im);
-- INST_TAG_END ------ End INSTANTIATION Template ------------

end Behavioral;