counter.xco

含有各类寄存器

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\Xilinx\OpenHard\HDL_file\counter_core
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc2s200e
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = pq208
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan2e
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Binary_Counter family Xilinx,_Inc. 6.0
# END Select
# BEGIN Parameters
CSET count_style=count_by_constant
CSET create_rpm=true
CSET output_width=8
CSET async_init_value=0
CSET threshold_0=false
CSET threshold_1=false
CSET synchronous_settings=none
CSET count_to_value=MAX
CSET threshold_1_value=MAX
CSET clock_enable=true
CSET threshold_0_value=MAX
CSET asynchronous_settings=clear
CSET ce_overrides=sync_controls_override_ce
CSET load=true
CSET set_clear_priority=clear_overrides_set
CSET component_name=counter
CSET count_by_value=1
CSET threshold_early=true
CSET restrict_count=false
CSET operation=up_down
CSET sync_init_value=0
CSET ce_override_for_load=false
CSET threshold_options=non_registered
CSET load_sense=active_high
# END Parameters
GENERATE