adder.vhd

含有各类寄存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--use work.ISCAS.all;

entity adder is
    Port ( a : 	in 	std_logic_vector(15 downto 0);
           b : 	in 	std_logic_vector(15 downto 0);
           Cin : 	in 	std_logic;
           sum : 	out 	std_logic_vector(15 downto 0);
           Cout : out 	std_logic);
end adder;

architecture behavioral of adder is

begin

process(a,b,Cin)
variable temp_sum : std_logic_vector(15 downto 0);
variable temp_Cout: std_logic_vector(16 downto 0);
--constant groupa: iarray(0 to 2) := (4,5,7);

begin 
temp_Cout(0) := Cin;
	 For i in 0 to 15 loop
	 	temp_sum(i ) := a(i )xor temp_Cout(i)xor b(i );
		temp_Cout(i+1) :=(a(i )and b(i )) or (temp_Cout(i) and (a(i ) or b(i )));
	 end loop;

sum <= not temp_sum;
Cout <= not temp_Cout(16);

end process; 

end behavioral;