tb_test_cy7c1062av33.vhd

Test bench for CY7C1062AV33

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_Test_CY7C1062AV33 IS
END tb_Test_CY7C1062AV33;
 
ARCHITECTURE behavior OF tb_Test_CY7C1062AV33 IS 
 
    COMPONENT Test_CY7C1062AV33
    PORT(
         CLOCK : IN  std_logic;
         RESET_n : IN  std_logic;
         CDE_ECRITURE : IN  std_logic;
         CDE_LECTURE : IN  std_logic;
         DATA_TEST_i : IN  std_logic_vector(31 downto 0);
         FPGA_PPC_LALE : OUT  std_logic;
         FPGA_PPC_SRAM_BAn : OUT  std_logic;
         FPGA_PPC_SRAM_BBn : OUT  std_logic;
         FPGA_PPC_SRAM_BCn : OUT  std_logic;
         FPGA_PPC_SRAM_BDn : OUT  std_logic;
         FPGA_PPC_SRAM_OEn : OUT  std_logic;
         FPGA_PPC_SRAM_WEn : OUT  std_logic;
         FPGA_PPC_SRAM_CE1n : OUT  std_logic;
         DATA_TEST_o : OUT  std_logic_vector(31 downto 0);
         FPGA_PPC_IO : INOUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLOCK : std_logic := '0';
   signal RESET_n : std_logic := '0';
   signal CDE_ECRITURE : std_logic := '0';
   signal CDE_LECTURE : std_logic := '0';
   signal DATA_TEST_i : std_logic_vector(31 downto 0) := (others => '0');

	--BiDirs
   signal FPGA_PPC_IO : std_logic_vector(31 downto 0);

 	--Outputs
   signal FPGA_PPC_LALE : std_logic;
   signal FPGA_PPC_SRAM_BAn : std_logic;
   signal FPGA_PPC_SRAM_BBn : std_logic;
   signal FPGA_PPC_SRAM_BCn : std_logic;
   signal FPGA_PPC_SRAM_BDn : std_logic;
   signal FPGA_PPC_SRAM_OEn : std_logic;
   signal FPGA_PPC_SRAM_WEn : std_logic;
   signal FPGA_PPC_SRAM_CE1n : std_logic;
   signal DATA_TEST_o : std_logic_vector(31 downto 0);
   signal MPC_GPIO_PD13 : std_logic;
   signal MPC_GPIO_PD19 : std_logic;
   signal MPC_GPIO_PD21 : std_logic;
   signal MPC_GPIO_PD23 : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Test_CY7C1062AV33 PORT MAP (
          CLOCK => CLOCK,
          RESET_n => RESET_n,
          CDE_ECRITURE => CDE_ECRITURE,
          CDE_LECTURE => CDE_LECTURE,
          DATA_TEST_i => DATA_TEST_i,
          FPGA_PPC_LALE => FPGA_PPC_LALE,
          FPGA_PPC_SRAM_BAn => FPGA_PPC_SRAM_BAn,
          FPGA_PPC_SRAM_BBn => FPGA_PPC_SRAM_BBn,
          FPGA_PPC_SRAM_BCn => FPGA_PPC_SRAM_BCn,
          FPGA_PPC_SRAM_BDn => FPGA_PPC_SRAM_BDn,
          FPGA_PPC_SRAM_OEn => FPGA_PPC_SRAM_OEn,
          FPGA_PPC_SRAM_WEn => FPGA_PPC_SRAM_WEn,
          FPGA_PPC_SRAM_CE1n => FPGA_PPC_SRAM_CE1n,
          DATA_TEST_o => DATA_TEST_o,
          FPGA_PPC_IO => FPGA_PPC_IO
        );
 

 
   CLOCK_process :process
   begin
		CLOCK <= '0';
		wait for 5ns;
		CLOCK <= '1';
		wait for 5ns;
   end process;
 

   stim_proc: process
   begin
		RESET_n <= '0';
		CDE_ECRITURE <= '0';
		DATA_TEST_i <= "01010101010101010101010101010101";
      wait for 20ns;	
		RESET_n <= '1';
		wait for 20ns;	
		RESET_n <= '1';
		wait for 20ns;	
		CDE_ECRITURE <= '1';
		wait for 10ns;
		CDE_ECRITURE <= '0';
		wait for 100ns;
		CDE_LECTURE <= '1';
		wait for 10ns;
		CDE_LECTURE <= '0';
		
      wait;
   end process;

END;