tb_moteur_test.vhd

来自「Test Bench for an engine code VHDL for C」· VHDL 代码 · 共 95 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_Moteur_test IS
END tb_Moteur_test;
 
ARCHITECTURE behavior OF tb_Moteur_test IS 
 
 
    COMPONENT Moteur_test
    PORT(
         CLOCK 					: IN  std_logic;
			RESET_MANUAL_n 		: IN  std_logic;
         FPGA_PPC_LALE 			: OUT std_logic;
         FPGA_PPC_SRAM_BAn 	: OUT std_logic;
         FPGA_PPC_SRAM_BBn 	: OUT std_logic;
         FPGA_PPC_SRAM_BCn 	: OUT std_logic;
         FPGA_PPC_SRAM_BDn 	: OUT std_logic;
         FPGA_PPC_SRAM_OEn 	: OUT std_logic;
         FPGA_PPC_SRAM_WEn		: OUT std_logic;
         FPGA_PPC_SRAM_CE1n 	: OUT std_logic;
         FPGA_PPC_IO 			: INOUT std_logic_vector(31 downto 0);
         MPC_GPIO_PD13 			: OUT std_logic;
			MPC_GPIO_PD19			: OUT std_logic;
			MPC_GPIO_PD21			: OUT std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLOCK : std_logic := '0';
	signal RESET_MANUAL_n : std_logic := '0';

	--BiDirs
   signal FPGA_PPC_IO : std_logic_vector(31 downto 0);

 	--Outputs
   signal FPGA_PPC_LALE : std_logic;
   signal FPGA_PPC_SRAM_BAn : std_logic;
   signal FPGA_PPC_SRAM_BBn : std_logic;
   signal FPGA_PPC_SRAM_BCn : std_logic;
   signal FPGA_PPC_SRAM_BDn : std_logic;
   signal FPGA_PPC_SRAM_OEn : std_logic;
   signal FPGA_PPC_SRAM_WEn : std_logic;
   signal FPGA_PPC_SRAM_CE1n : std_logic;
   signal MPC_GPIO_PD13 : std_logic;
	signal MPC_GPIO_PD19 : std_logic;
	signal MPC_GPIO_PD21 : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Moteur_test PORT MAP (
          CLOCK => CLOCK,
			 RESET_MANUAL_n => RESET_MANUAL_n,
          FPGA_PPC_LALE => FPGA_PPC_LALE,
          FPGA_PPC_SRAM_BAn => FPGA_PPC_SRAM_BAn,
          FPGA_PPC_SRAM_BBn => FPGA_PPC_SRAM_BBn,
          FPGA_PPC_SRAM_BCn => FPGA_PPC_SRAM_BCn,
          FPGA_PPC_SRAM_BDn => FPGA_PPC_SRAM_BDn,
          FPGA_PPC_SRAM_OEn => FPGA_PPC_SRAM_OEn,
          FPGA_PPC_SRAM_WEn => FPGA_PPC_SRAM_WEn,
          FPGA_PPC_SRAM_CE1n => FPGA_PPC_SRAM_CE1n,
          FPGA_PPC_IO => FPGA_PPC_IO,
          MPC_GPIO_PD13 => MPC_GPIO_PD13,
			 MPC_GPIO_PD19 => MPC_GPIO_PD19,
			 MPC_GPIO_PD21 => MPC_GPIO_PD21
        );

	
	
   CLOCK_process :process
   begin
		CLOCK <= '0';
		wait for 5ns;
		CLOCK <= '1';
		wait for 5ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		FPGA_PPC_IO 			<= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
		RESET_MANUAL_n 		<= '0';
		wait until falling_edge(CLOCK);
      RESET_MANUAL_n <= '1';
		wait;
   end process;

END;