moteur_test.vhd

Engine for a test memory CY7C1062AV33

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Moteur_test is port (
		CLOCK : IN  std_logic;
		RESET_MANUAL_n : IN  std_logic;
		FPGA_PPC_LALE : OUT  std_logic;
		FPGA_PPC_SRAM_BAn : OUT  std_logic;
		FPGA_PPC_SRAM_BBn : OUT  std_logic;
		FPGA_PPC_SRAM_BCn : OUT  std_logic;
		FPGA_PPC_SRAM_BDn : OUT  std_logic;
		FPGA_PPC_SRAM_OEn : OUT  std_logic;
		FPGA_PPC_SRAM_WEn : OUT  std_logic;
		FPGA_PPC_SRAM_CE1n : OUT  std_logic;
		FPGA_PPC_IO : INOUT  std_logic_vector(31 downto 0);
		MPC_GPIO_PD13 			: out std_logic;
		MPC_GPIO_PD19			: out std_logic;
		MPC_GPIO_PD21			: out std_logic
	);
end Moteur_test;

architecture Moteur_test of Moteur_test is

	COMPONENT DCM1 PORT(
		CLKIN_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK2X_OUT : OUT std_logic
		);
	END COMPONENT;
	
	COMPONENT ILA1 PORT(
		 CLK : in STD_LOGIC; 
		 CONTROL : inout STD_LOGIC_VECTOR ( 35 downto 0 ); 
		 TRIG0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
		 DATA : in STD_LOGIC_VECTOR ( 99 downto 0 ) 
	  );
	END COMPONENT;

	COMPONENT ICON1 PORT(
		 CONTROL0 : inout STD_LOGIC_VECTOR ( 35 downto 0 ) 
	  );
	END COMPONENT;

	COMPONENT Test_CY7C1062AV33 PORT(
		CLOCK : IN  std_logic;
		RESET_n : IN  std_logic;
		CDE_ECRITURE : IN  std_logic;
		CDE_LECTURE : IN  std_logic;
		DATA_TEST_i : IN  std_logic_vector(31 downto 0);
		FPGA_PPC_LALE : OUT  std_logic;
		FPGA_PPC_SRAM_BAn : OUT  std_logic;
		FPGA_PPC_SRAM_BBn : OUT  std_logic;
		FPGA_PPC_SRAM_BCn : OUT  std_logic;
		FPGA_PPC_SRAM_BDn : OUT  std_logic;
		FPGA_PPC_SRAM_OEn : OUT  std_logic;
		FPGA_PPC_SRAM_WEn : OUT  std_logic;
		FPGA_PPC_SRAM_CE1n : OUT  std_logic;
		DATA_TEST_o : OUT  std_logic_vector(31 downto 0);
		FPGA_PPC_IO : INOUT  std_logic_vector(31 downto 0)
		);
	END COMPONENT;
	 
	signal start_power : integer range 0 to 10000 := 0;
	signal cnt : integer range 0 to 240 := 0;	-- compteur pour s閝uencer les lectures 閏ritures

	 
	signal compteur_test : std_logic_vector(19 downto 0);
	 
	signal reset : std_logic := '0';
	signal scde_ecriture : std_logic;
	signal scde_lecture : std_logic;
	signal sdata_test_i : std_logic_vector(31 downto 0);
	signal sdata_test_o : std_logic_vector(31 downto 0);
	 
	signal led : std_logic := '1';
	
	-- Pour ChipScop
	signal clock_100MHz : std_logic;
	signal clock_200MHz : std_logic;
	signal control_bus : std_logic_vector (35 downto 0);
	signal trig0 : std_logic_vector (7 downto 0);
	signal data : std_logic_vector (99 downto 0);


begin

	Inst_DCM1: DCM1 PORT MAP(
		CLKIN_IN => CLOCK,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => clock_100MHz,
		CLK2X_OUT => clock_200MHz
	);

	Inst_ILA1: ILA1 PORT MAP(
		CLK => clock_200MHz,
		CONTROL => control_bus,
		TRIG0 => trig0,
		DATA => data
	  );

	Inst_ICON1: ICON1 PORT MAP(
		CONTROL0 => control_bus
	  );

inst_Test_CY7C1062AV33 : Test_CY7C1062AV33 port map (
	CLOCK => clock_100MHz,
	RESET_n => reset,
	CDE_ECRITURE => scde_ecriture,
	CDE_LECTURE => scde_lecture,
	DATA_TEST_i => sdata_test_i,
	FPGA_PPC_LALE => FPGA_PPC_LALE,
	FPGA_PPC_SRAM_BAn => FPGA_PPC_SRAM_BAn,
	FPGA_PPC_SRAM_BBn => FPGA_PPC_SRAM_BBn,
	FPGA_PPC_SRAM_BCn => FPGA_PPC_SRAM_BCn,
	FPGA_PPC_SRAM_BDn => FPGA_PPC_SRAM_BDn,
	FPGA_PPC_SRAM_OEn => FPGA_PPC_SRAM_OEn,
	FPGA_PPC_SRAM_WEn => FPGA_PPC_SRAM_WEn,
	FPGA_PPC_SRAM_CE1n => FPGA_PPC_SRAM_CE1n,
	DATA_TEST_o => sdata_test_o,
	FPGA_PPC_IO => FPGA_PPC_IO
	);
	
	
process (clock_100MHz)
	begin
		if ( rising_edge(clock_100MHz) ) then
			if (start_power > 9) then
				reset <= '1';
			else
				reset <= '0';
				start_power <= start_power +1;
			end if;
		end if;
end process;

process (clock_100MHz, reset)
	begin
	if (reset = '0') then
		trig0	<= "00000000" ;
	elsif ( rising_edge(clock_100MHz) ) then
		data(0) <= reset;
		data(1) <= scde_ecriture;
		data(2) <= scde_lecture;
		data(3) <= led;

		data(35 downto 4) <= sdata_test_i;
		data(67 downto 36) <= sdata_test_o;
		data(99 downto 68) <= FPGA_PPC_IO;
		
		if(RESET_MANUAL_n = '0') then
			trig0	<= "10000000" ;
		elsif(compteur_test = "00000000000000000000") then
			trig0	<= "00000001" ;
		elsif(compteur_test = "00000000000000000001") then
			trig0	<= "00000010" ;
		elsif(compteur_test = "00000000000000100000") then
			trig0	<= "00000100" ;
		elsif(compteur_test = "01111111111111111111") then
			trig0	<= "00001000" ;
		else
			trig0	<= "00000000" ;
		end if;
		
	end if;
end process;

process (clock_100MHz ,reset, RESET_MANUAL_n)
	begin

		if (reset = '0') then
			cnt <= 0;
			scde_ecriture <= '0';
			scde_lecture <= '0';
			sdata_test_i <= x"00000000";
			compteur_test <= "00000000000000000000";
			led <= '1';
		elsif(RESET_MANUAL_n = '0') then
			cnt <= 0;
			scde_ecriture <= '0';
			scde_lecture <= '0';
			sdata_test_i <= x"00000000";
			compteur_test <= "00000000000000000000";
			
		elsif ( rising_edge(clock_100MHz) and  compteur_test < "10000000000000000000") then
		
			if(cnt=10) then
				scde_ecriture <= '1';
				sdata_test_i <= "000000000000" & compteur_test;
			elsif(cnt=120) then
				scde_lecture <= '1';			
			elsif(cnt=130) then
				if(not sdata_test_o = sdata_test_i) then
				else
					led <= '0';
				end if;
			elsif(cnt=239) then
				compteur_test <= compteur_test + 1;
			else
				scde_ecriture <= '0';
				scde_lecture <= '0';
			end if;
			
			if(cnt/=240) then
				cnt <= cnt + 1;
			else
				cnt <= 0;
			end if;
		
		end if;

	if(compteur_test = "00000000000000000000") then
		MPC_GPIO_PD19 <= '1';
	else
		MPC_GPIO_PD19 <= '0';
	end if;

	if(compteur_test = "10000000000000000000") then
		MPC_GPIO_PD21 <= '1';
	else
		MPC_GPIO_PD21 <= '0';
	end if;

end process;




MPC_GPIO_PD13 <= led ;

end Moteur_test;