tb_date.vhd

TEst bench of an increment date

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-- Company: 
-- Engineer:
--
-- Create Date:   13:56:47 03/12/2009
-- Design Name:   
-- Module Name:   C:/ISE/Date/date/tb_date.vhd
-- Project Name:  date
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: TOP_DATE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_date IS
END tb_date;
 
ARCHITECTURE behavior OF tb_date IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT TOP_DATE
    PORT(
         CLOCK : IN  std_logic;
         DATE : OUT  std_logic_vector(23 downto 0);
         RESET_n : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLOCK : std_logic := '0';
   signal RESET_n : std_logic := '0';

 	--Outputs
   signal DATE : std_logic_vector(23 downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: TOP_DATE PORT MAP (
          CLOCK => CLOCK,
          DATE => DATE,
          RESET_n => RESET_n
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
 
   clock_process :process
   begin
		CLOCK <= '0';
		wait for 5 ns;
		CLOCK <= '1';
		wait for 5 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		RESET_n <= '0';
      wait for 100 ns;	
		RESET_n <= '1';
		
      wait;
   end process;

END;