top_date.vhd

Code to have an incremante date

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:50:43 03/12/2009 
-- Design Name: 
-- Module Name:    TOP_DATE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP_DATE is
    Port ( CLOCK : in  STD_LOGIC;
           DATE : out  STD_LOGIC_VECTOR (23 downto 0);
           RESET_n : in  STD_LOGIC
			);
end TOP_DATE;

architecture Behavioral of TOP_DATE is

signal micro : std_logic_vector(6 downto 0) := "0000000";
signal sDATE : std_logic_vector (23 downto 0);

signal raz	: std_logic := '0';

begin

DATE <= sDATE ;

process (CLOCK, RESET_n )
begin
	if ( RESET_n = '0' ) then
		sDATE  <= x"0E7EF0";	-- Pour les tests, on se place