4luxianzeqi.txt

一个4路选择器的东西 程序 源代码都在 大家可以看看是不是可以用用 帮帮忙吧

抢答鉴别模块QDJB参考程序：
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY QDJB IS
  PORT(CLR:  IN STD_LOGIC; 
       A, B, C, D:  IN STD_LOGIC; 
       A1,B1,C1,D1:  OUT STD_LOGIC; 
       STATES:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); 
END ENTITY QDJB; 
ARCHITECTURE ART OF QDJB IS
  CONSTANT W1:  STD_LOGIC_VECTOR(3 DOWNTO 0):="0001"; 
  CONSTANT W2:  STD_LOGIC_VECTOR(3 DOWNTO 0):="0010"; 
  CONSTANT W3:  STD_LOGIC_VECTOR(3 DOWNTO 0):="0100"; 
  CONSTANT W4:  STD_LOGIC_VECTOR(3 DOWNTO 0):="1000"; 
  BEGIN
  PROCESS(CLR,A,B,C,D) IS
  BEGIN
IF CLR='1' THEN STATES<="0000";a1<='0';b1<='0';c1<='0';d1<='0'; 
    ELSIF (A='1'AND B='0'AND C='0'AND D='0') THEN
      A1<='1';  B1<='0'; C1<='0'; D1<='0'; STATES<=W1; 
    ELSIF (A='0'AND B='1'AND C='0'AND D='0') THEN
      A1<='0';  B1<='1'; C1<='0'; D1<='0'; STATES<=W2; 
    ELSIF (A='0'AND B='0'AND C='1'AND D='0') THEN
      A1<='0';  B1<='0'; C1<='1'; D1<='0'; STATES<=W3; 
    ELSIF (A='0'AND B='0'AND C='0'AND D='1') THEN
      A1<='0';  B1<='0'; C1<='0'; D1<='1'; STATES<=W4; 
    END IF; 
  END PROCESS; 
END ARCHITECTURE ART;
计分模块JFQ参考程序：
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY JFQ IS
  PORT(RST: IN STD_LOGIC; 
       ADD: IN STD_LOGIC; 
       CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
       AA2,AA1,AA0,BB2,BB1,BB0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); 
      CC2,CC1,CC0,DD2,DD1,DD0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); 
END ENTITY JFQ ; 
ARCHITECTURE ART OF JFQ IS
  BEGIN
  PROCESS(RST,ADD,CHOS) IS
    VARIABLE POINTS_A2,POINTS_A1: STD_LOGIC_VECTOR(3 DOWNTO 0); 
    VARIABLE POINTS_B2,POINTS_B1: STD_LOGIC_VECTOR(3 DOWNTO 0); 
    VARIABLE POINTS_C2,POINTS_C1: STD_LOGIC_VECTOR(3 DOWNTO 0); 
    VARIABLE POINTS_D2,POINTS_D1: STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN
    IF (ADD'EVENT AND ADD='1')  THEN
       IF RST='1' THEN
         POINTS_A2:="0001"; POINTS_A1:="0000"; 
         POINTS_B2:="0001"; POINTS_B1:="0000"; 
         POINTS_C2:="0001"; POINTS_C1:="0000"; 
         POINTS_D2:="0001"; POINTS_D1:="0000"; 
       ELSIF CHOS="0001" THEN
          IF POINTS_A1="1001" THEN
             POINTS_A1:="0000"; 
             IF POINTS_A2="1001" THEN
                POINTS_A2:="0000"; 
             ELSE 
                POINTS_A2:=POINTS_A2+1; 
             END IF; 
          ELSE
             POINTS_A1:=POINTS_A1+1; 
          END IF; 
       ELSIF CHOS="0010" THEN
          IF POINTS_B1="1001" THEN
             POINTS_B1:="0000"; 
             IF POINTS_B2="1001" THEN
                POINTS_B2:="0000"; 
             ELSE
                POINTS_B2:=POINTS_B2+1; 
             END IF; 
          ELSE
             POINTS_B1:=POINTS_B1+1; 
          END IF; 
       ELSIF CHOS="0100" THEN
          IF POINTS_C1="1001" THEN
             POINTS_C1:="0000"; 
             IF POINTS_C2="1001" THEN
                POINTS_C2:="0000"; 
             ELSE
                POINTS_C2:=POINTS_C2+1; 
             END IF; 
          ELSE
             POINTS_C1:=POINTS_C1+1; 
          END IF; 
        ELSIF CHOS="1000" THEN
          IF POINTS_D1="1001" THEN
             POINTS_D1:="0000"; 
             IF POINTS_D2="1001" THEN
                POINTS_D2:="0000";
             ELSE
                POINTS_D2:=POINTS_D2+1; 
             END IF; 
          ELSE
             POINTS_D1:=POINTS_D1+1; 
          END IF; 
         END IF; 
      END IF; 
    AA2<=POINTS_A2; AA1<=POINTS_A1; AA0<="0000"; 
    BB2<=POINTS_B2; BB1<=POINTS_B1; BB0<="0000"; 
    CC2<=POINTS_C2; CC1<=POINTS_C1; CC0<="0000"; 
    DD2<=POINTS_D2; DD1<=POINTS_D1; DD0<="0000"; 
  END PROCESS; 
END ARCHITECTURE ART;
抢答计时模块JSQ参考程序：
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY JSQ IS
  PORT(CLR,LDN,EN,CLK: IN STD_LOGIC; 
       TA,TB:IN STD_LOGIC; --zhishu
       QA:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --ge wei
       QB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --shi wei
END ENTITY JSQ; 
ARCHITECTURE ART OF JSQ IS
  SIGNAL DA:STD_LOGIC_VECTOR(3 DOWNTO 0); 
  SIGNAL DB:STD_LOGIC_VECTOR(3 DOWNTO 0); 
  BEGIN
  PROCESS(TA,TB,CLR) IS
    BEGIN
    IF CLR='1' THEN
     DA<="0000"; 
     DB<="0000"; 
    ELSE
IF  TA='1'  THEN
     DA<=DA+'1' ; 
    END IF; 
    IF  TB='1' THEN
      DB<=DB+'1'; 
    END IF; 
   END IF; 
 END PROCESS; 
 PROCESS(CLK) IS
   VARIABLE TMPA:STD_LOGIC_VECTOR(3 DOWNTO 0); 
   VARIABLE TMPB:STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN
    IF CLR='1' THEN TMPA:="0000"; TMPB:="0110"; 
    ELSIF CLK'EVENT AND CLK='1' THEN
        IF LDN='1' THEN TMPA:=DA; TMPB:=DB; --zhishu kongzhi
        ELSIF EN='1' THEN
           IF TMPA="0000" THEN
             TMPA:="1001"; 
              IF TMPB="0000" THEN TMPB:="0110"; 
              ELSE TMPB:=TMPB-1; 
END IF; 
           ELSE TMPA:=TMPA-1; 
           END IF; 
        END IF; 
    END IF; 
    QA<=TMPA; QB<=TMPB; 
  END PROCESS; 
END ARCHITECTURE ART;
译码器模块YMQ参考程序：
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY YMQ IS
  PORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
       DOUT7:  OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); 
END YMQ; 
ARCHITECTURE ART OF YMQ IS
BEGIN
  PROCESS(AIN4)
    BEGIN
    CASE AIN4 IS
    WHEN "0000"=>DOUT7<="0000001"; 	    --0
    WHEN "0001"=>DOUT7<="1001111"; 		--1
    WHEN "0010"=>DOUT7<="0010010"; 		--2
    WHEN "0011"=>DOUT7<="0000110"; 		--3
    WHEN "0100"=>DOUT7<="1001100"; 		--4
    WHEN "0101"=>DOUT7<="0100100"; 		--5
    WHEN "0110"=>DOUT7<="0100000"; 		--6
    WHEN "0111"=>DOUT7<="0001111"; 		--7
    WHEN "1000"=>DOUT7<="0000000"; 		--8
    WHEN "1001"=>DOUT7<="0000100"; 		--9
    WHEN OTHERS=>DOUT7<="1111111"; 
    END CASE; 
  END PROCESS; 
END ARCHITECTURE ART;