clk_devide.vhd

来自「基于CPLD的4X4键盘输入+液晶显示程序」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk_devide is
    port(
        clk     :    in    std_logic;
		clkout	:out 	  std_logic);
end clk_devide;

architecture a of clk_devide is
    signal clkfrq    :    std_logic;
    signal cntfrq    :    integer range 0 to 330000;
begin
    process(clk, clkfrq) -- 晶振为66.667MHz，进行33333分频产生扫描时钟（1000Hz)
    begin
        if clk'event and clk = '1' then
            if cntfrq = 30000 then 
                cntfrq <= 0;
                clkfrq <= not clkfrq;
            else
                cntfrq <= cntfrq + 1;
            end if;
        end if;
    end process;
	clkout<=clkfrq;
end;