input.map.rpt

基于CPLD的4X4键盘输入+液晶显示程序

;     -- Total 1-input functions    ; 30                     ;
;     -- Total 0-input functions    ; 2                      ;
; Combinational cells for routing   ; 0                      ;
; Total registers                   ; 107                    ;
; Total logic cells in carry chains ; 31                     ;
; I/O pins                          ; 22                     ;
; Maximum fan-out node              ; clk_devide:inst|clkout ;
; Maximum fan-out                   ; 47                     ;
; Total fan-out                     ; 981                    ;
; Average fan-out                   ; 3.45                   ;
+-----------------------------------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                            ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name       ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
; |TODAC                     ; 262 (1)     ; 107          ; 0          ; 22   ; 0            ; 155 (1)      ; 54 (0)            ; 53 (0)           ; 31 (0)          ; |TODAC                    ;
;    |clk_devide:inst|       ; 45 (45)     ; 20           ; 0          ; 0    ; 0            ; 25 (25)      ; 12 (12)           ; 8 (8)            ; 19 (19)         ; |TODAC|clk_devide:inst    ;
;    |keyboard4_4:inst2|     ; 73 (73)     ; 26           ; 0          ; 0    ; 0            ; 47 (47)      ; 3 (3)             ; 23 (23)          ; 8 (8)           ; |TODAC|keyboard4_4:inst2  ;
;    |led4bits7seg:inst4|    ; 143 (143)   ; 61           ; 0          ; 0    ; 0            ; 82 (82)      ; 39 (39)           ; 22 (22)          ; 4 (4)           ; |TODAC|led4bits7seg:inst4 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 107   ;
; Number of registers using Synchronous Clear  ; 12    ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 41    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 72    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; led4bits7seg:inst4|g[4]                ; 5       ;
; led4bits7seg:inst4|BW[4]               ; 5       ;
; led4bits7seg:inst4|QW[4]               ; 4       ;
; led4bits7seg:inst4|SW[4]               ; 3       ;
; led4bits7seg:inst4|q[4]                ; 3       ;
; led4bits7seg:inst4|b[4]                ; 3       ;
; led4bits7seg:inst4|W[4]                ; 5       ;
; led4bits7seg:inst4|s[4]                ; 3       ;
; Total number of inverted registers = 8 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; Yes        ; |TODAC|keyboard4_4:inst2|scnlin[0]     ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |TODAC|keyboard4_4:inst2|count2[7]     ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |TODAC|led4bits7seg:inst4|STATE[0]     ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |TODAC|led4bits7seg:inst4|timecount[0] ;
; 26:1               ; 6 bits    ; 102 LEs       ; 72 LEs               ; 30 LEs                 ; Yes        ; |TODAC|led4bits7seg:inst4|data[0]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/QuartusII Project/INPUT-TO_LCD/input.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jul 29 14:37:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off input -c input
Info: Found 2 design units, including 1 entities, in source file CLK_DEVIDE.vhd
    Info: Found design unit 1: clk_devide-a
    Info: Found entity 1: clk_devide
Info: Found 2 design units, including 1 entities, in source file keyboard4_4.vhd
    Info: Found design unit 1: keyboard4_4-keyboard4_4_arch
    Info: Found entity 1: keyboard4_4
Info: Found 1 design units, including 1 entities, in source file TODAC.bdf
    Info: Found entity 1: TODAC
Info: Found 2 design units, including 1 entities, in source file led4bits7seg.vhd
    Info: Found design unit 1: led4bits7seg-rt1
    Info: Found entity 1: led4bits7seg
Info: Found 2 design units, including 1 entities, in source file bcdto7seg.vhd
    Info: Found design unit 1: converter-a
    Info: Found entity 1: converter
Info: Elaborating entity "TODAC" for the top level hierarchy
Info: Elaborating entity "led4bits7seg" for hierarchy "led4bits7seg:inst4"
Info: (10035) Verilog HDL or VHDL information at led4bits7seg.vhd(17): object "temp" declared but not used
Info: (10035) Verilog HDL or VHDL information at led4bits7seg.vhd(18): object "count" declared but not used
Info: (10035) Verilog HDL or VHDL information at led4bits7seg.vhd(19): object "islock" declared but not used
Info: (10035) Verilog HDL or VHDL information at led4bits7seg.vhd(20): object "num" declared but not used
Warning: VHDL Process Statement warning at led4bits7seg.vhd(31): signal "ENTER" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at led4bits7seg.vhd(32): signal "q" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at led4bits7seg.vhd(32): signal "b" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at led4bits7seg.vhd(32): signal "s" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at led4bits7seg.vhd(32): signal "g" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "clk_devide" for hierarchy "clk_devide:inst"
Info: Elaborating entity "keyboard4_4" for hierarchy "keyboard4_4:inst2"
Warning: Reduced register "led4bits7seg:inst4|LCDSTATE[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "led4bits7seg:inst4|LCDSTATE[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "led4bits7seg:inst4|LCDSTATE[1]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "writeORread" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 284 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 15 output pins
    Info: Implemented 262 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sun Jul 29 14:37:36 2007
    Info: Elapsed time: 00:00:07