vga_controller.v

用于fpga的sopc的ip核

module	VGA_Controller(	//	Host Side

                                         iRGB_INDEX,
						oAddress,
						oCoord_X,
						oCoord_Y,
						//	VGA Side
                                         oRGB_INDEX,
						oVGA_H_SYNC,
						oVGA_V_SYNC,
						oVGA_SYNC,
						oVGA_BLANK,
						oVGA_CLOCK,
						//	Control Signal
						iCLK_27,
						iRST_N	,
                                         oclk_27
                                           );

//
//	Horizontal Parameter	( Pixel )
parameter	H_SYNC_CYC	=	96;
parameter	H_SYNC_BACK	=	48;
parameter	H_SYNC_ACT	=	640;	//	646
parameter	H_SYNC_FRONT=	16;
parameter	H_SYNC_TOTAL=	800;
//	Virtical Parameter		( Line )
parameter	V_SYNC_CYC	=	2;
parameter	V_SYNC_BACK	=	32;
parameter	V_SYNC_ACT	=	480;	//	484
parameter	V_SYNC_FRONT=	11;
parameter	V_SYNC_TOTAL=	525;
//	Start Offset
parameter	X_START		=	148;
parameter	Y_START		=	34;



//	Host Side
output	reg	[15:0]	oAddress;
output     oclk_27;
output	reg	[9:0]	oCoord_X;
output	reg	[9:0]	oCoord_Y;
input         [7:0]  iRGB_INDEX;
//	VGA Side
output        [8:0]  oRGB_INDEX;
output	reg			oVGA_H_SYNC;
output	reg			oVGA_V_SYNC;
output				oVGA_SYNC;
output				oVGA_BLANK;
output				oVGA_CLOCK;
//	Control Signal
input				iCLK_27;
input				iRST_N;

//	Internal Registers and Wires
reg		[9:0]		H_Cont;
reg		[9:0]		V_Cont;
wire				mCLK;
assign  oclk_27=iCLK_27;
assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
assign	oVGA_SYNC	=	1'b0;

assign	oRGB_INDEX[8:0]	=	(	H_Cont>=X_START+230+4	&& H_Cont<X_START+H_SYNC_ACT-230+4 &&
						V_Cont>=Y_START+150 	&& V_Cont<Y_START+V_SYNC_ACT-150 )
						?		{1'b0,iRGB_INDEX}	:	9'h100	;              //
/*assign	oRGB_INDEX[8]	=	(	H_Cont>=X_START+220 	&& H_Cont<X_START+H_SYNC_ACT-220 &&
						V_Cont>=Y_START+140 	&& V_Cont<Y_START+V_SYNC_ACT-140 )
						?		0	:	1'b1	;              */

//	Pixel LUT Address Generator
always@(posedge mCLK or negedge iRST_N)                 //在此处控制屏幕现实范围
begin
	if(!iRST_N)
	begin
		oCoord_X	<=	0;
		oCoord_Y	<=	0;
		oAddress	<=	0;
	end
	else
	begin
		if(	H_Cont>=X_START+230 && H_Cont<=X_START+H_SYNC_ACT-230 &&
			V_Cont>=Y_START+150 && V_Cont<Y_START+V_SYNC_ACT-150 )
		begin
			oCoord_X	<=	H_Cont-X_START-230;
			oCoord_Y	<=	V_Cont-Y_START-150;
			oAddress	<=	oCoord_Y*180+oCoord_X;
		end
	end
end

//	Cursor Generator
//	VGA Pixel Clock 25.175 MHz
VGA_PLL		PLL1 	(	.areset(~iRST_N),
						.inclk0(iCLK_27),
						.c0(mCLK),
						.c1(oVGA_CLOCK)	);

//	H_Sync Generator, Ref. 25.175 MHz Clock
always@(posedge mCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		H_Cont		<=	0;
		oVGA_H_SYNC	<=	0;
	end
	else
	begin
		//	H_Sync Counter
		if( H_Cont < H_SYNC_TOTAL )
		H_Cont	<=	H_Cont+1;
		else
		H_Cont	<=	0;
		//	H_Sync Generator
		if( H_Cont < H_SYNC_CYC )
		oVGA_H_SYNC	<=	0;
		else
		oVGA_H_SYNC	<=	1;
	end
end

//	V_Sync Generator, Ref. H_Sync
always@(posedge mCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		V_Cont		<=	0;
		oVGA_V_SYNC	<=	0;
	end
	else
	begin
		//	When H_Sync Re-start
		if(H_Cont==0)
		begin
			//	V_Sync Counter
			if( V_Cont < V_SYNC_TOTAL )
			V_Cont	<=	V_Cont+1;
			else
			V_Cont	<=	0;
			//	V_Sync Generator
			if(	V_Cont < V_SYNC_CYC )
			oVGA_V_SYNC	<=	0;
			else
			oVGA_V_SYNC	<=	1;
		end
	end
end

endmodule