class.ptf

用于fpga的sopc的ip核

                           PORT oVGA_BLANK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oVGA_CLOCK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iCLK_27
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iRST_N
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "VGA_Controller";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER h_sync_cyc
                        {
                           parameter_name = "H_SYNC_CYC";
                           type = "integer";
                           default_value = "96";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER h_sync_back
                        {
                           parameter_name = "H_SYNC_BACK";
                           type = "integer";
                           default_value = "48";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER h_sync_act
                        {
                           parameter_name = "H_SYNC_ACT";
                           type = "integer";
                           default_value = "640";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER h_sync_front
                        {
                           parameter_name = "H_SYNC_FRONT";
                           type = "integer";
                           default_value = "16";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER h_sync_total
                        {
                           parameter_name = "H_SYNC_TOTAL";
                           type = "integer";
                           default_value = "800";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER v_sync_cyc
                        {
                           parameter_name = "V_SYNC_CYC";
                           type = "integer";
                           default_value = "2";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER v_sync_back
                        {
                           parameter_name = "V_SYNC_BACK";
                           type = "integer";
                           default_value = "32";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER v_sync_act
                        {
                           parameter_name = "V_SYNC_ACT";
                           type = "integer";
                           default_value = "480";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER v_sync_front
                        {
                           parameter_name = "V_SYNC_FRONT";
                           type = "integer";
                           default_value = "11";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER v_sync_total
                        {
                           parameter_name = "V_SYNC_TOTAL";
                           type = "integer";
                           default_value = "525";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER x_start
                        {
                           parameter_name = "X_START";
                           type = "integer";
                           default_value = "148";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER y_start
                        {
                           parameter_name = "Y_START";
                           type = "integer";
                           default_value = "34";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
         FILE VGA_NIOS_CTRL.v
         {
            file_mod = "Sun Jul 30 14:56:54 CST 2006";
            quartus_map_start = "Sun Jul 30 15:00:29 CST 2006";
            quartus_map_finished = "Sun Jul 30 15:00:33 CST 2006";
            #found 1 valid modules
            WRAPPER VGA_NIOS_CTRL
            {
               CLASS VGA_NIOS_CTRL
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "C:/Documents and Settings/Administrator/桌面/显卡2/VGA_NIOS_CTRL.v";
                        }
                     }
                     top_module_name = "VGA_NIOS_CTRL";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "VGA_NIOS_CTRL";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT oDATA
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iDATA
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iADDR
                           {
                              width = "16";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iWR
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iRD
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iCS
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iCLK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iRST_N
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT VGA_R
                           {
                              width = "10";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT VGA_G
                           {
                              width = "10";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT VGA_B
                           {
                              width = "10";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT VGA_HS
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oclk_27
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";