class.ptf

用于fpga的sopc的ip核

      {
         title = "xianka4 - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>xianka4 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2006.07.30.15:03:22";
               }
               TEXT 
               {
                  title = "Class name: xianka4";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: xianka4";
               }
               TEXT 
               {
                  title = "Component Group: xianka4";
               }
               GROUP parameters
               {
                  title = "Parameters";
                  layout = "form";
                  align = "left";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "5.10";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
         HDL_PARAMETER base
         {
            parameter_name = "BASE";
            type = "integer";
            default_value = "16'b1001110001000000";
            editable = "0";
            tooltip = "";
         }
      }
      SW_FILES 
      {
      }
      built_on = "2006.07.30.15:03:22";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE Img_RAM.v
         {
            file_mod = "Thu Jul 20 19:14:52 CST 2006";
            quartus_map_start = "Sun Jul 30 15:00:23 CST 2006";
            quartus_map_finished = "Sun Jul 30 15:00:25 CST 2006";
            #found 1 valid modules
            WRAPPER Img_RAM
            {
               CLASS Img_RAM
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "C:/Documents and Settings/Administrator/桌面/显卡2/Img_RAM.v";
                        }
                     }
                     top_module_name = "Img_RAM";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "Img_RAM";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT data
                           {
                              width = "8";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT rdaddress
                           {
                              width = "16";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT rdclock
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT wraddress
                           {
                              width = "16";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT wrclock
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT wren
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT q
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "Img_RAM";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
         FILE VGA_Controller.v
         {
            file_mod = "Sun Jul 30 14:56:58 CST 2006";
            quartus_map_start = "Sun Jul 30 15:00:26 CST 2006";
            quartus_map_finished = "Sun Jul 30 15:00:28 CST 2006";
            #found 1 valid modules
            WRAPPER VGA_Controller
            {
               CLASS VGA_Controller
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "C:/Documents and Settings/Administrator/桌面/显卡2/VGA_Controller.v";
                        }
                     }
                     top_module_name = "VGA_Controller";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "VGA_Controller";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT oAddress
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oclk_27
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oCoord_X
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oCoord_Y
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT iRGB_INDEX
                           {
                              width = "8";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oRGB_INDEX
                           {
                              width = "9";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oVGA_H_SYNC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oVGA_V_SYNC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT oVGA_SYNC
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }