veriwell.log

6 bit wallace reduction in verilog

VeriWell for Win32 HDL     <Version 2.0.10>    Tue Feb 01 09:05:24 2000

  This is a free version of the VeriWell for Win32 Simulator
  Distribute this freely; call 1-800-VERIWELL for ordering information
  See the file "!readme.1st" for more information

  Copyright (c) 1996 Wellspring Solutions, Inc.
            All rights reserved


Memory Available: 0
Entering Phase I...
Compiling source file : wallace.v
Compiling source file : wallace_test.v
The size of this model is [9%, 5%] of the capacity of the free version

Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
   test

C1> .
a=40;b11;prod= 440
0 Errors, 0 Warnings, Memory Used: 134888
Compile time = 0.0, Load time = 0.0, Simulation time = 0.1

Normal exit
Thank you for using VeriWell for Win32