wallace_test.v

来自「6 bit wallace reduction in verilog」· Verilog 代码 · 共 13 行

module test;
reg [5:0] a,b;
wire [11:0] prod;

wallace w(a,b,prod);
initial
begin
a=1000;b=11;
end
initial
$monitor("a=%d;b%d;prod=%d",a,b,prod);

endmodule