testbench.v

6 bit dadda tree reduction code -- verilog

module dadda_test();

reg [5:0] a,b;
wire [11:0] prod;
wire [7:0] c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11;


dadda instance(a,b,s,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11);
initial
begin

a=54;
b=37;


end


initial
begin
$monitor("a=%b,b=%b,prod=%b,c0=%b,c1=%b,c2=%b,c3=%b,c4=%b,c5=%b,c6=%b,c7=%b,c8=%b,c9=%b,c10=%b,c11=%b",a,b,prod,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11);

end

endmodule