clock.cmp.qrpt

用verilog实现的数字跑表

[||Compilation Report||Timing Analyzer||Clock Hold: 'clk']
COLUMN_WIDTHS=269L,154L,132L,41L,41L,82L,99L,86L,
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Compilation Report||Timing Analyzer||Timing Analyzer Summary]
COLUMN_WIDTHS=309L,218L,57L,223L,132L,154L,213L,224L,42L,
OUTPUT_SECTION=1
PAGE_ORIENTATION=0