pwm_task_logic.v

这是一个完整的pwm ip 核

/****************************************Copyright (c)**************************************************
**                               Guangzou ZLG-MCU Development Co.,LTD.
**                                      graduate school
**                                 http://www.zlgmcu.com
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			pwm_task_logic.v
** Last modified Date:	2005-12-13
** Last Version:		1.0
** Descriptions:		PWM logic
**------------------------------------------------------------------------------------------------------
** Created by:			LiuYingbin
** Created date:		2005-12-13
** Version:				1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/

module pwm_task_logic(
	clock,
	pwm_enable,
	reset_n, 
	clock_divide,
	duty_cycle,
	pwm_out
	);

	//Inputs
	input clock;					//Input Clock to be divided
	input [31:0] clock_divide;	//Clock Divide value
	input [31:0] duty_cycle;	//Duty Cycle vale
	input pwm_enable;			//Enable signal
	input reset_n;				//Reset

	//Outputs
	output pwm_out;				//PWM output

//Signal Declarations	
reg [31:0] counter;		//PWM Internal Counter
reg pwm_out;			//PWM output
	
//PWM Counter Process
always @(posedge clock or negedge reset_n)         
begin
	if (~reset_n)begin
		counter <= 0;
	end
	else if(pwm_enable)
	begin
		if (counter >= clock_divide)
			counter <= 0;
		else 
			counter <= counter + 1;
	end
end

//PWM Comparitor
always @(posedge clock or negedge reset_n)      
begin
	if (~reset_n)begin
		pwm_out <= 0;
	end
	else 
	begin
		if (pwm_enable & (counter >= duty_cycle))
			pwm_out <= 1'b1;
		else
			pwm_out <= 1'b0;
	end
end

	
endmodule