fpround.vhd

一个32位元的浮点数加法器

-- Modified by Nomad 2007,03 v1
-- Modified by Nomad 2007,4,09 v2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY FPround IS
   GENERIC( 
      --SIG_width : integer := 26 --23SIG+3
      SIG_width : integer := 28
   );
   PORT( 
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
   );
END FPround ;

ARCHITECTURE FPround OF FPround IS
BEGIN
	EXP_out <= EXP_in;

PROCESS(SIG_in)
BEGIN
--   IF (SIG_in(0)='0') THEN
--		SIG_out <= SIG_in;
--   ELSE
-- 		SIG_out <= (SIG_in(SIG_width-1 DOWNTO 1) + 1) & '0';
--	END IF;
--END PROCESS;

--END FPround;

   IF (SIG_in(2)='0') THEN
		SIG_out <= SIG_in;
   ELSE
 		SIG_out <= (SIG_in(SIG_width-1 DOWNTO 3) + 1) & "000";
	END IF;
END PROCESS;

END FPround;