fpselcomplement.vhd

来自「一个32位元的浮点数加法器」· VHDL 代码 · 共 37 行

--modified 2007,03 v1
--modified 2007,04,09 v2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;


ENTITY FPselComplement IS
   GENERIC( 
      SIG_width : integer := 28
   );
   PORT( 
      SIG_in  : IN     std_logic_vector (SIG_width DOWNTO 0);
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
   );
END FPselComplement ;

ARCHITECTURE FPselComplement OF FPselComplement IS
BEGIN

	EXP_out <= EXP_in;

	PROCESS(SIG_in)
	BEGIN
		IF (SIG_in(SIG_width) = '1') THEN
			SIG_out <= (NOT SIG_in(SIG_width-1 DOWNTO 0) + 1);
		ELSE
			SIG_out <= SIG_in(SIG_width-1 DOWNTO 0);
		END IF;
	END PROCESS;

END FPselComplement;