unpackfp.vhd

一个32位元的浮点数加法器

--32bits FLP unpack
--1s_8I_23F
--by Fen Chih Yen 2007_03_27

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY UnpackFP IS
   PORT( 
      FP    : IN     std_logic_vector (31 DOWNTO 0);
      SIG   : OUT    std_logic_vector (31 DOWNTO 0);
      EXP   : OUT    std_logic_vector (7 DOWNTO 0);
      SIGN  : OUT    std_logic;
      isNaN : OUT    std_logic;
      isINF : OUT    std_logic;
      isZ   : OUT    std_logic;
      isDN  : OUT    std_logic
   );
END UnpackFP ;

ARCHITECTURE UnpackFP OF UnpackFP IS
	SIGNAL exp_int : std_logic_vector(7 DOWNTO 0);
	SIGNAL sig_int : std_logic_vector(22 DOWNTO 0);
	SIGNAL expZ, expFF, sigZ : std_logic;
BEGIN
	exp_int <= FP(30 DOWNTO 23);
	sig_int <= FP(22 DOWNTO 0);

	SIGN <= FP(31);
	EXP <= exp_int;
	SIG(22 DOWNTO 0) <= sig_int;

	expZ <= '1' WHEN (exp_int="00000000") ELSE '0';
	expFF <= '1' WHEN (exp_int="11111111") ELSE '0';

	sigZ <= '1' WHEN (sig_int="00000000000000000000000") ELSE '0';

	isNaN <= expFF AND (NOT sigZ);
	isINF <= expFF AND sigZ;
	isZ <= expZ AND sigZ;
	isDN <= expZ AND (NOT sigZ);

	-- Restore hidden 1.ffff when not zero or denormal
--	SIG(22) <= NOT expZ;
  SIG(23) <= NOT expZ;
  
	SIG(31 DOWNTO 24) <= (OTHERS => '0');
END UnpackFP;