ps2.map.qmsg

FPGA的PS2口接口程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 08 20:34:03 2009 " "Info: Processing started: Thu Jan 08 20:34:03 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PS2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PS2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PS2 " "Info: Found entity 1: PS2" {  } { { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_scanC.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file data_scanC.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_scanC " "Info: Found entity 1: data_scanC" {  } { { "data_scanC.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/data_scanC.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "convert.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file convert.v" { { "Info" "ISGN_ENTITY_NAME" "1 convert " "Info: Found entity 1: convert" {  } { { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "segmain.v(14) " "Warning (10268): Verilog HDL information at segmain.v(14): Always Construct contains both blocking and non-blocking assignments" {  } { { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 14 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain " "Info: Found entity 1: segmain" {  } { { "segmain.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/segmain.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PS2 " "Info: Elaborating entity \"PS2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "PS2 " "Warning: Processing legacy GDF or BDF entity \"PS2\" with Max+Plus II bus and instance naming rules" {  } { { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst8 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst8\"" {  } { { "PS2.bdf" "inst8" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 216 136 320 312 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_scanC data_scanC:inst " "Info: Elaborating entity \"data_scanC\" for hierarchy \"data_scanC:inst\"" {  } { { "PS2.bdf" "inst" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 40 112 248 168 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "convert convert:inst7 " "Info: Elaborating entity \"convert\" for hierarchy \"convert:inst7\"" {  } { { "PS2.bdf" "inst7" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 40 376 528 168 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_FULL_CASE_DIRECTIVE_EFFECTIVE" "convert.v(61) " "Warning (10208): Verilog HDL Case Statement warning: implemented Verilog HDL full_case synthesis attribute at convert.v(61) -- differences between design synthesis and simulation may occur" {  } { { "convert.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/convert.v" 61 0 0 } }  } 0 10208 "Verilog HDL Case Statement warning: implemented Verilog HDL full_case synthesis attribute at %1!s! -- differences between design synthesis and simulation may occur" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "78leddata\[7\] VCC " "Warning (13410): Pin \"78leddata\[7\]\" stuck at VCC" {  } { { "PS2.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.bdf" { { 240 336 512 256 "78leddata\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "22 22 " "Info: 22 registers lost all their fanouts during netlist optimizations. The first 22 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[15\] " "Info: Register \"segmain:inst8\|count\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[16\] " "Info: Register \"segmain:inst8\|count\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[17\] " "Info: Register \"segmain:inst8\|count\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[18\] " "Info: Register \"segmain:inst8\|count\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[19\] " "Info: Register \"segmain:inst8\|count\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[20\] " "Info: Register \"segmain:inst8\|count\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[21\] " "Info: Register \"segmain:inst8\|count\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[22\] " "Info: Register \"segmain:inst8\|count\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[23\] " "Info: Register \"segmain:inst8\|count\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[24\] " "Info: Register \"segmain:inst8\|count\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[25\] " "Info: Register \"segmain:inst8\|count\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[26\] " "Info: Register \"segmain:inst8\|count\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[27\] " "Info: Register \"segmain:inst8\|count\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[28\] " "Info: Register \"segmain:inst8\|count\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[29\] " "Info: Register \"segmain:inst8\|count\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[30\] " "Info: Register \"segmain:inst8\|count\[30\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[31\] " "Info: Register \"segmain:inst8\|count\[31\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[32\] " "Info: Register \"segmain:inst8\|count\[32\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[33\] " "Info: Register \"segmain:inst8\|count\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[34\] " "Info: Register \"segmain:inst8\|count\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[35\] " "Info: Register \"segmain:inst8\|count\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "segmain:inst8\|count\[36\] " "Info: Register \"segmain:inst8\|count\[36\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "204 " "Info: Implemented 204 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "188 " "Info: Implemented 188 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.map.smsg " "Info: Generated suppressed messages file D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/PS2_v/PS2.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 08 20:34:08 2009 " "Info: Processing ended: Thu Jan 08 20:34:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}